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Current density check for layout design

Hello,

I want to check if my routing in the layout are well designed to carry the currents in the circuit and have no current density problem, it is kind of routing reliability check for layout

Thank you

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Frank Wiedmann over 4 years ago

You might want to take a look at support.cadence.com/.../articleattachmentportal
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Andrew Beckett over 4 years ago in reply to Frank Wiedmann

There is also the Virtuoso Electrically Aware Design tool (this is for in-design EM analysis) and Voltus-Fi XL tool too (a higher capacity signoff tool). I've made those links to the relevant RAKs.

Andrew.
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Andrew Beckett over 4 years ago in reply to Frank Wiedmann

There is also the Virtuoso Electrically Aware Design tool (this is for in-design EM analysis) and Voltus-Fi XL tool too (a higher capacity signoff tool). I've made those links to the relevant RAKs.

Andrew.
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Senan over 4 years ago in reply to Andrew Beckett

Thank you very much Andrew for your help
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