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Getting Flat Outputs while implementing a 6 Bit Flash ADC using VerilogA.

Kulmani

Hi,

I am trying to model a 6 Bit Flash ADC using VerilogA.

Here is the code : 

`include "constants.vams"
`include "disciplines.vams"

module ADC(vout, vclk,vin);
output [5:0] vout;
electrical [5:0] vout;
input vclk;
electrical vclk;
input vin;
electrical vin;
real vdout[0:5];
real trise = 1;
real tfall = 1;
real tdel = 1;


real vth = 0.9;
real samp;
integer i,vd;
real lsb = 0.015;

analog begin
@(cross(V(vclk) - vth,+1)) samp = V(vin);
vd = (samp - 1.8 )/ lsb;
$display ("The value of samp is %g",samp);
$display ("The value of vd is %g",vd);
$display ("The value of time is %g",$abstime);


for (i=0; i < 6 ; i=i+1 ) begin
vdout[i] = vd%2;
vd=vd/2;
$display ("Value of vdout is %g", vdout[i]);
end

V(vout[0]) <+ transition(vdout[0],tdel,trise,tfall );
V(vout[1]) <+ transition(vdout[1],tdel,trise,tfall );
V(vout[2]) <+ transition(vdout[2],tdel,trise,tfall );
V(vout[3]) <+ transition(vdout[3],tdel,trise,tfall );
V(vout[4]) <+ transition(vdout[4],tdel,trise,tfall );
V(vout[5]) <+ transition(vdout[5],tdel,trise,tfall );
end

endmodule

In output i am getting all the flat lines resting at 0 when i am giving a 100ns period to the applied clock i.e vclk, when i print the conversion values i am getting vdout as per my Vin ( kept 2.1 ) analog voltage in my run log but the waveform still shows it 0 . Can anyone tell me what is wrong with the code or if anyone has a working model of Flash ADC i would be thankful.

Regards,

Kulmani

Parents

  • Kulmani,

    You have trise, tdel and tfall set to 1 - that's 1 second. So nothing is going to output for 1 second, and the rise and fall times of the transition are huge (1 second).

    So it's no wonder it doesn't work! 

    If you change the values to (say) 1n (for all three), then it should work.

    Andrew

  • in reply to Andrew Beckett

    Thank you so much Andrew for pointing out the error. That helped a lot. Now i am able to simulate the ADC with correct results. Since i am a beginner in veriloga and i want to model other blocks like DAC,LDO,VCO,PLLs using veriloga, can you suggest some good references to look forward for help apart from the veriloga manual. It would really ease off things for me. Thanks again for the help. Really appreciate what you do. 

    Kulmani

  • in reply to Kulmani
    Kulmani said:
    can you suggest some good references to look forward for help apart from the veriloga manual.

    This book is pretty good: The Designer's Guide to Verilog-AMS

    The e-book is available from the publishers at http://springer.com - unfortunately it's quite expensive (not unusual for specialist books), but it's pretty good (even though it was published in 2004).

    You could also take advantage of the free online training at http://support.cadence.com - go to Learning->Online Courses in the middle and search for Verilog-A. You'll then find a course called "Analog Modeling with Verilog-A vSPECTRE17.1" . 

    Nowadays Cadence's  "Internet Learning Series" training courses are available for free on the support web site.

    Andrew

  • in reply to Andrew Beckett

    Thank you for all these references. I am sure this will help me a lot. 

Reply Children
  • in reply to Kulmani

    Hi Andrew, Sorry to bother you again. I was able to successfully implement the ADC with your help and was able to verify it at Block Level. Now when i am trying to replace the model at the Full Chip level i see that my ADC inputs ( which are coming from a Differential Amp ) are getting distorted ( the signals seem to go way below/above common mode ) and hence the ADC output is coming totally weird. I tried putting up a huge resistance/Cap in my model but that also didn't help. I am unable to understand what is going on and how shall i correct it . if you can help me out here that would be great.

  • in reply to Kulmani

    I'm not sure how you expect me to help here - I have no visibility of what you've done so I really cannot guess what might be wrong in your circuit or model.

    I suggest you contact customer support or speak to your supervisor?

    Andrew

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