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Getting Flat Outputs while implementing a 6 Bit Flash ADC using VerilogA.

Kulmani

Hi,

I am trying to model a 6 Bit Flash ADC using VerilogA.

Here is the code : 

`include "constants.vams"
`include "disciplines.vams"

module ADC(vout, vclk,vin);
output [5:0] vout;
electrical [5:0] vout;
input vclk;
electrical vclk;
input vin;
electrical vin;
real vdout[0:5];
real trise = 1;
real tfall = 1;
real tdel = 1;


real vth = 0.9;
real samp;
integer i,vd;
real lsb = 0.015;

analog begin
@(cross(V(vclk) - vth,+1)) samp = V(vin);
vd = (samp - 1.8 )/ lsb;
$display ("The value of samp is %g",samp);
$display ("The value of vd is %g",vd);
$display ("The value of time is %g",$abstime);


for (i=0; i < 6 ; i=i+1 ) begin
vdout[i] = vd%2;
vd=vd/2;
$display ("Value of vdout is %g", vdout[i]);
end

V(vout[0]) <+ transition(vdout[0],tdel,trise,tfall );
V(vout[1]) <+ transition(vdout[1],tdel,trise,tfall );
V(vout[2]) <+ transition(vdout[2],tdel,trise,tfall );
V(vout[3]) <+ transition(vdout[3],tdel,trise,tfall );
V(vout[4]) <+ transition(vdout[4],tdel,trise,tfall );
V(vout[5]) <+ transition(vdout[5],tdel,trise,tfall );
end

endmodule

In output i am getting all the flat lines resting at 0 when i am giving a 100ns period to the applied clock i.e vclk, when i print the conversion values i am getting vdout as per my Vin ( kept 2.1 ) analog voltage in my run log but the waveform still shows it 0 . Can anyone tell me what is wrong with the code or if anyone has a working model of Flash ADC i would be thankful.

Regards,

Kulmani

Parents

  • Dear Kulmani,

    Within the Cadence ahdl Library (included in your Cadence installation - refer to Figure 1 -there is an 8 bit ADC which uses 8 input comparators whose name is adc_8bit. Hence, this in effect models a flash converter. You might consider using this in lieu of your veriloga model - or perhaps modify it to meet your needs. From the header information in the 

    // This ADC comprises 8 comparators. An input voltage is compared to

    // half the reference voltage. If the input exceeds it, bit 7 is set and half

    // the reference voltage is subtracted. If not, bit 7 is assigned zero

    // and no voltage is subtracted from the input. Bit 6 is found by doing an

    // equivalent operation comparing double the adjusted input voltage coming

    // from the first comparator with half the reference voltage. Similarly

    // all the other bits are found.

    //

    // Mismatch effects in the comparator reference voltages can be modeled

    // setting 'mismatch' to a non-zero value. The maximum mismatch on a 

    // comparator's reference voltage is then +/-'mismatch' percent of

    // that voltage's nominal value.

    //

    Shawn

    Figure 1

  • in reply to ShawnLogan

    Thank you Shawn for your reply. That helped a ton for references. But i am not sure that they have implemented a Flash ADC there as they are substracting the reference voltage and the doubling up the voltage whereas in a Flash ADC we compare the analog inputs with references to generate a decimal thermometric code and then encode it into desired bits. Found the could a bit confusing or maybe i couldn't understand well. But thanks for pointing out the library, i can take a lot of references from there now :)

    Kulmani

  • in reply to Kulmani

    Dear Kulmani,

    Kulmani said:
    But i am not sure that they have implemented a Flash ADC there as they are substracting the reference voltage and the doubling up the voltage whereas in a Flash ADC we compare the analog inputs with references to generate a decimal thermometric code

    You are absolutely correct...I did realize that but thought since it was an "ideal" model of a converter it might accomplish what you needed. Perhaps you wanted access to the thermometer code as the output. Obviously, that implementation will not provide a thermometer code - it's topology is more of a SAR. In any case, the veriloga code examples in the library are helpful and am glad you found the library!

    Thank you for the update Kulman!

    Shawn

  • in reply to ShawnLogan

    Thank you for your time Shawn.

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