Global nets in the extracted view

This seems a bit odd. I'm wondering if there might be some inherited connections (net expressions) on pins of your devices and the default values of those are causing global nets to be created - I can't think why else it might happen. Since I assume you can't share the design here, you probably need to speak to customer support.

Andrew

Andrew Beckett I went through https://groups.google.com/g/comp.cad.cadence/c/Dc6en4z3yig?pli=1 which is a conversation you had a few years back. Seems like this is something I am facing as well!

My unit CMOS inverter is as follows (unfortunately I am not allowed to share any other designs publicly)

The way I created these pins is Create -> Pin ;

Name: vdd

Direction: inputOutput

Usage: Schematic

Signal Type: power

and everything else was left untouched. I am using IC6.1.8-64b .

Similarly ;

Name: gnd

Direction: inputOutput

Usage: Schematic

Signal Type: ground

the pins "in" and "out" are given the directions "input" and "output" respectively. Their signal type is 'signal' instead of 'power' or 'ground'.

Once this is done, I check and save the schematic and then Launch -> Layout XL -> create new ; Connectivity -> Generate all from sources; Create Labels for pins with the same layer and purpose (ME1 Drawing).

Then Place -> Pin Placement ; Here is where I see that the pins are vdd! instead of vdd and gnd! instead of gnd.

After this, I just routed the nets and performed DRC and LVS checks. Later I proceeded with the av_extraction and generated the post layout netlist using Quantus (Assura).

Once this is done, I head back to the schematic, Launch -> ADE L and setup the av_extracted view before the others so that the parasitic are considered. (Is this required to generate the Netlist using ADE L -> Simulation -> Netlist -> Create?Because I already have the spice file which Quantus gave me.)

Now what I need to do is Take these to Liberate and characterize them as a library so that I can port them into a synthesis solution and go ahead wit some synthesis runs.

I am using UMC's 0.18u M FDK for all of this. My university has access to this through the Europractice consoritum. I will file the Case on customer support if I am not able to get help from here after this detailed explanation of the scenario, but the Pandemic is in it's peak here in India and the University is closed. Going through COS will be a time consuming process.

thank you so much for your valuable time in advance, I hope I can get some help from here

That other thread (on the comp.cad.cadence news group) isn't really relevant as that's about having global pins in the schematic, which you don't have. What is odd is that the schematic has normal pins, and they are converted to global pins (for the supplies only) on layout generation. 

Can you make your schematic window current (click in it somewhere) and then in the CIW enter:

geGetEditCellView()~>nets~>name
geGetEditCellView()~>nets~>term~>name
geGetEditCellView()~>nets~>aliases

Thanks,

Andrew

That other thread (on the comp.cad.cadence news group) isn't really relevant as that's about having global pins in the schematic, which you don't have. What is odd is that the schematic has normal pins, and they are converted to global pins (for the supplies only) on layout generation. 

Can you make your schematic window current (click in it somewhere) and then in the CIW enter:

geGetEditCellView()~>nets~>name
geGetEditCellView()~>nets~>term~>name
geGetEditCellView()~>nets~>aliases

Thanks,

Andrew

Andrew Beckett said:

Can you make your schematic window current (click in it somewhere) and then in the CIW enter:

geGetEditCellView()~>nets~>name
geGetEditCellView()~>nets~>term~>name
geGetEditCellView()~>nets~>aliases

Here's what the CIW says:

In text:

geGetEditCellView()~>nets~>name
("vdd" "out" "gnd" "in")
geGetEditCellView()~>nets~>term~>name
("vdd" "out" "gnd" "in")
geGetEditCellView()~>nets~>aliases
(("vdd")
("out")
("gnd")
("in")
)

Here's what it says when I make the layout window current:

In text:

geGetEditCellView()~>nets~>term~>name
("out" "gnd!" "in" "vdd!")
geGetEditCellView()~>nets~>name
("out" "gnd!" "in" "vdd!")
geGetEditCellView()~>nets~>term~>name
("out" "gnd!" "in" "vdd!")
geGetEditCellView()~>nets~>aliases
(("out")
("gnd!")
("in")
("vdd!")
)

Nothing obvious so far to explain why global nets have been used on the layout. A stab in the dark, but can you give the results of these with the layout window as the current window?

geGetEditCellView()~>instances~>master~>nets~>name

geGetEditCellView()~>instances~>master~>terminals~>name

geGetEditCellView()~>instances~>master~>terminals~>net~>name

BTW - I wouldn't worry about spending time capturing the images of the output - text is fine (and is better, as it's searchable and can be copied).

Thanks.

Andrew

Andrew Beckett said:

geGetEditCellView()~>instances~>master~>nets~>name

geGetEditCellView()~>instances~>master~>terminals~>name

geGetEditCellView()~>instances~>master~>terminals~>net~>name

Here you go!

geGetEditCellView()~>instances~>master~>nets~>name
(("G" "S" "D" "B" "G_mustGroup_1"
"S_mustGroup_0" "D_mustGroup_1"
)
("G" "S" "D" "B" "G_mustGroup_1"
"S_mustGroup_0" "D_mustGroup_1"
)
)
geGetEditCellView()~>instances~>master~>terminals~>name
(("G" "S" "D" "B" "G_mustGroup_1"
"S_mustGroup_0" "D_mustGroup_1"
)
("G" "S" "D" "B" "G_mustGroup_1"
"S_mustGroup_0" "D_mustGroup_1"
)
)
geGetEditCellView()~>instances~>master~>terminals~>net~>name
(("G" "S" "D" "B" "G_mustGroup_1"
"S_mustGroup_0" "D_mustGroup_1"
)
("G" "S" "D" "B" "G_mustGroup_1"
"S_mustGroup_0" "D_mustGroup_1"
)
)

Andrew Beckett said:

BTW - I wouldn't worry about spending time capturing the images of the output - text is fine (and is better, as it's searchable and can be copied).

Okay!

thanks

Nothing unusual there either. I would suggest you report this to Europractice (you can find the contact details by searching for the europractice software service). In fact here it is http://www.europractice.stfc.ac.uk/contact_us.html

if they can’t solve it, they will contact us. 

Andrew