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Global nets in the extracted view

iamKarthikBK

When I design a cell using the Virtuoso Schematic Editor, I name nets as local nets (a, b, vdd, gnd, and so on). When I draw the layout, these nets become global automatically (vdd! and gnd!). I later get errors telling that net gnd! is shorted to gnd.

How to avoid nets becoming global?

Parents

  • I had a similar problem recently. What had happened was that someone had created copies of some logic PCells, both schematic and layout, and added explicit vdd and vss pins instead of using vdd! and vss!. Then they edited the layout removing the  vdd! and vss! and placing the new vdd and vss pins there instead.

    All seems fine right? LVS and DRC clean, perfect. Unfortunately, somewhere in the layout properties it retained the idea that it had inherited connections, so any higher cell in the hierarchy that instanced the newly copied cell would get vdd! and vss! brought into layout whenever you either generated all from source or updated pins. Again, simply delete them and it always came LVS and DRC clean, so no issue, but an annoyance.

    The solution was to find the offending cell, for example the inverter described below, create a NEW blank layout (no memory of inherited connections), copy the drawn layers over to the new layout and save that, replacing the original with the weird inherited connections.

Reply

  • I had a similar problem recently. What had happened was that someone had created copies of some logic PCells, both schematic and layout, and added explicit vdd and vss pins instead of using vdd! and vss!. Then they edited the layout removing the  vdd! and vss! and placing the new vdd and vss pins there instead.

    All seems fine right? LVS and DRC clean, perfect. Unfortunately, somewhere in the layout properties it retained the idea that it had inherited connections, so any higher cell in the hierarchy that instanced the newly copied cell would get vdd! and vss! brought into layout whenever you either generated all from source or updated pins. Again, simply delete them and it always came LVS and DRC clean, so no issue, but an annoyance.

    The solution was to find the offending cell, for example the inverter described below, create a NEW blank layout (no memory of inherited connections), copy the drawn layers over to the new layout and save that, replacing the original with the weird inherited connections.

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