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Accessing simulation variables in verilog-a without passed parameter?

In Verilog-AMS, I am able to access simulation variables in a module by using:

cds_globals.<name of variable>

I'm trying to keep my design as clean as possible, and I don't want to add a parameter to the veriloga view (the other views do not need a passed parameter). Is there a way to access simulation variables without passing them as a parameter? I don't want to use the AMS simulator.

Thanks.

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Andrew Beckett over 4 years ago

You can access global parameters (e.g. ADE Design Variables) using:

(* cds_inherited_parameter *) parameter real rfactor=0.0;

in the Verilog-A. The magic attribute before the parameter definition marks it as access it from the global parameter rfactor in this case rather than it being passed in.

Hope that helps!

Andrew
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MikeVP over 4 years ago in reply to Andrew Beckett

Thank you very much. I will try.

Could you kindly point me to the documentation on this?
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MikeVP over 4 years ago in reply to Andrew Beckett

Thank you very much. I will try.

Could you kindly point me to the documentation on this?
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Andrew Beckett over 4 years ago in reply to MikeVP

/path/to/SPECTREinstallation/bin/cdnshelp then search for cds_inherited_parameter

This is in the Verilog-A Reference manual <SPECTREinstDir>/doc/veriaref/veriaref.pdf

There's also discussion (and a link to the documentation) in this article.

Andrew
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