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PLL + PSS + PNOISE convergence

HoWei

After reading most of the documentation about how to setup PSS for ring-oscillators, etc. I was able to simulate the ring-VCO with an subsequent div-by-2 in PSS with PNOISE and got reasonable results.

All the blocks are analog (spice/spectre), only the control signals are generated from Verilog-A blocks. I do see some warnings about the Verilo-A blocks.

- fvco=480M, fdiv2=240MHz --> beat-freq=240MHz, conservative, 600 harmonics, tstab=500n

- autonomous circuit: osc-node+ is the ringo-vco output net

- cmin=4fF ( to have not ideal sharp edges)

The next step towards a full PLL feedback loop simulation was to add another div-by-12 frequency divider in series to the div-by-2 --> did not achieve convergence yet, but tested the following settings

- beat-freq=20MHz, tstab=500n, maxstep=1ps (or none)

- osc-node+ is either ringvco-output(480MHz) or fbdiv12-output(20MHz), but none did converge the PSS simulation

- trap vs. gear2only

The Conv norm value is sometimes below 1, but still does not converge.

1. Any idea what I can do to achieve convergence ?

2. A collerague told me (from his experience) to set the beat-freq to 20MHz/3=6.6667MHz, but he could not tell me why this would be advantageous - do you have any idea )

The final goal is to simulate the complete PLL, which will then be a driven circuit with a reference signal (no osc-node+ required).

But first I want to achieve convergence for "ring-vco+divby2+divby12".

Attached is the spectre.out (at least I drag and dropped it into the editor, but cannot see it)  ... ?

Parents

  • There was a similar question here a little while back where the beat frequency was something like 20M/3 because there was a sub-harmonic in the divider (I forget the details and haven't searched). The key is to understand whether the divide-by-12 has any sub-harmonics below 1/12 of the input frequency - if it does, then the beat frequency must take that into account. It rather depends on how that divide by 12 is achieved.

    I can't see the log file either (try inserting it via Insert->Image/video/file instead).

    Note too that when you do get to running the whole PLL, you should not use "oscillator" mode any more since the circuit then ceases to be autonomous (the output frequency is a harmonic of the driven input frequency) - doing so would also likely lead to convergence failure since you would be trying to solve an unknown that isn't unknown.

    The best way to get support for this kind of issue is via customer support. Trying to read between the lines to infer the problem in the forums is rather hard for such issues, and it also takes more time than I (at least) have time for in my spare moments.

    Andrew

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  • There was a similar question here a little while back where the beat frequency was something like 20M/3 because there was a sub-harmonic in the divider (I forget the details and haven't searched). The key is to understand whether the divide-by-12 has any sub-harmonics below 1/12 of the input frequency - if it does, then the beat frequency must take that into account. It rather depends on how that divide by 12 is achieved.

    I can't see the log file either (try inserting it via Insert->Image/video/file instead).

    Note too that when you do get to running the whole PLL, you should not use "oscillator" mode any more since the circuit then ceases to be autonomous (the output frequency is a harmonic of the driven input frequency) - doing so would also likely lead to convergence failure since you would be trying to solve an unknown that isn't unknown.

    The best way to get support for this kind of issue is via customer support. Trying to read between the lines to infer the problem in the forums is rather hard for such issues, and it also takes more time than I (at least) have time for in my spare moments.

    Andrew

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