PLL + PSS + PNOISE convergence

There was a similar question here a little while back where the beat frequency was something like 20M/3 because there was a sub-harmonic in the divider (I forget the details and haven't searched). The key is to understand whether the divide-by-12 has any sub-harmonics below 1/12 of the input frequency - if it does, then the beat frequency must take that into account. It rather depends on how that divide by 12 is achieved.

I can't see the log file either (try inserting it via Insert->Image/video/file instead).

Note too that when you do get to running the whole PLL, you should not use "oscillator" mode any more since the circuit then ceases to be autonomous (the output frequency is a harmonic of the driven input frequency) - doing so would also likely lead to convergence failure since you would be trying to solve an unknown that isn't unknown.

The best way to get support for this kind of issue is via customer support. Trying to read between the lines to infer the problem in the forums is rather hard for such issues, and it also takes more time than I (at least) have time for in my spare moments.

Andrew

Hi Andrew,

you are right: after investigating the feedback-divider architecture (inherited from a colleague) I found that inside the divby12 are much smaller frequencies are generated --> this is where the 20MHz/3 frequency originates from. 

I know that this kind of problems are hard to support. For the sake of completeness and help, I will document my findings in this post - it might help others.

And I contacted customer support 1 week ago - no response yet.

By the way, the post you mentioned (some months ago) is the one I was looking for - opened by a colleague an discussion the same circuit !

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/47897/hb-analysis-on-pll/1373897#1373897

After reading the above mentioned discussion and reading about transient "checkpoint and restart", I am not clear if the PSS simulation can reuse transient simulation results.

As Shawn mentioned in the linked discussion above, there might be a way to start PSS with transient simulation results in steady state.

Is this doable ?

Can you provide me a tutorial/docu/link ?

I searched the forum, but did not find any proper material ...

No, PSS can't reuse transient results. You can use the save and restart with PSS, but the checkpoint needs to have been saved by the same analysis (PSS) - so you could run a stab, use the save* options to save one or more checkpoints, and restart from that. You just can't mix analyses.

Andrew

Regarding the definition of "steady state solutions" for PSS - attached are the internal signals of the div-by-15 circuit.

Would you consider the marked signals as periodic steady state ?

Their frequency-components might possibly not be a multiple of the lowest frequnency on top of the graph.

If this is the case, the beat note needs to be the greatest common divider of the two lowest frequencies, right ?

It would also not hurt to use a much lower beatfrequency, e.g. lowest frequency / 4 - of course it would increase the tstab-time.

Those two signals with arrows appear to have the same repeating period (at least from a visual inspection). What's needed is for all signals in the circuit to be able to fit an integer multiple of their period into the beat period. Put another way, if the frequency of each signal is 1/period (of course), the beat frequency needs to be the greatest common divisor of all frequencies in the circuit.

Andrew 

Yes, the repeating period is the same. 

The fact that there are longer high-levels every 4th or 8th edge will not affect the PSS steady state - thats what I read from your answer.

Great, the divider circuit now converges in PSS with different settings. with a clock input as a driven circuit.

Next I want to put a VCO at the input of the divider. The VCO (~480MHz) will operate close to a multiple integer (N=90) of the beat-freq=16/3MHz=5.333MHz.

As the VCO is a autonomous circuit, I need to define proper osc-nodes +/-, so

1. Where shall I select the osc-nodes - at the ring-vco output (480MHz) or at the divider-output (16MHz) or at the divider internal node with lowest freqeuncy (5.333MHz) ?

2. Will the PSS adjust its harmonics and beat-frequency to the VCO steady state frequency (e.g. 475,37546MHz) and converge with this frequency ?

And a question related to PNOISE:

When selecting the harmonic for the Pnoise result (relative offset phase-noise in dBc/Hz) - is the 1st harmonic the beat-frequency (~5.333MHz) or is it the VCO oscillation frequency (~480MHz) ?

Bthw. finally Cadence support contacted me today about my opened ticket - thats great !

Dear HoWei,

HoWei said:

1. Where shall I select the osc-nodes - at the ring-vco output (480MHz) or at the divider-output (16MHz) or at the divider internal node with lowest freqeuncy (5.333MHz) ?

I am not sure if you happened to examine either of the following very helpful application notes written to provide guidance on the proper use of pss settings in the presence of dividers:

support.cadence.com/.../ArticleAttachmentPortal

and

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nTyUEAU&pageName=ArticleContent

Both recommend, as makes sense, utilizing the lowest frequency (common) as the basis for the pss analysis as it requires there be an integral number of periods of all periodic waveforms to converge.

HoWei said:

2. Will the PSS adjust its harmonics and beat-frequency to the VCO steady state frequency (e.g. 475,37546MHz) and converge with this frequency ?

Yes.

HoWei said:

When selecting the harmonic for the Pnoise result (relative offset phase-noise in dBc/Hz) - is the 1st harmonic the beat-frequency (~5.333MHz) or is it the VCO oscillation frequency (~480MHz) ?

Since you are specifying the oscillation frequency as the minimum common periodic frequency, the harmonic in the pss analysis referred to as 1 is the lowest common frequency - or I believe 5.33 MHz in your specific case.

I hope this is useful to you HoWei.

Shawn