Stats

  • Locked Locked
  • Replies 17
  • Subscribers 125
  • Views 24550
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

PLL + PSS + PNOISE convergence

HoWei

After reading most of the documentation about how to setup PSS for ring-oscillators, etc. I was able to simulate the ring-VCO with an subsequent div-by-2 in PSS with PNOISE and got reasonable results.

All the blocks are analog (spice/spectre), only the control signals are generated from Verilog-A blocks. I do see some warnings about the Verilo-A blocks.

- fvco=480M, fdiv2=240MHz --> beat-freq=240MHz, conservative, 600 harmonics, tstab=500n

- autonomous circuit: osc-node+ is the ringo-vco output net

- cmin=4fF ( to have not ideal sharp edges)

The next step towards a full PLL feedback loop simulation was to add another div-by-12 frequency divider in series to the div-by-2 --> did not achieve convergence yet, but tested the following settings

- beat-freq=20MHz, tstab=500n, maxstep=1ps (or none)

- osc-node+ is either ringvco-output(480MHz) or fbdiv12-output(20MHz), but none did converge the PSS simulation

- trap vs. gear2only

The Conv norm value is sometimes below 1, but still does not converge.

1. Any idea what I can do to achieve convergence ?

2. A collerague told me (from his experience) to set the beat-freq to 20MHz/3=6.6667MHz, but he could not tell me why this would be advantageous - do you have any idea )

The final goal is to simulate the complete PLL, which will then be a driven circuit with a reference signal (no osc-node+ required).

But first I want to achieve convergence for "ring-vco+divby2+divby12".

Attached is the spectre.out (at least I drag and dropped it into the editor, but cannot see it)  ... ?

Parents

  • Regarding the definition of "steady state solutions" for PSS - attached are the internal signals of the div-by-15 circuit.

    Would you consider the marked signals as periodic steady state ?

    Their frequency-components might possibly not be a multiple of the lowest frequnency on top of the graph.

    If this is the case, the beat note needs to be the greatest common divider of the two lowest frequencies, right ?

    It would also not hurt to use a much lower beatfrequency, e.g. lowest frequency / 4 - of course it would increase the tstab-time.

     

Reply

  • Regarding the definition of "steady state solutions" for PSS - attached are the internal signals of the div-by-15 circuit.

    Would you consider the marked signals as periodic steady state ?

    Their frequency-components might possibly not be a multiple of the lowest frequnency on top of the graph.

    If this is the case, the beat note needs to be the greatest common divider of the two lowest frequencies, right ?

    It would also not hurt to use a much lower beatfrequency, e.g. lowest frequency / 4 - of course it would increase the tstab-time.

     

Children
  • in reply to HoWei

    Those two signals with arrows appear to have the same repeating period (at least from a visual inspection). What's needed is for all signals in the circuit to be able to fit an integer multiple of their period into the beat period. Put another way, if the frequency of each signal is 1/period (of course), the beat frequency needs to be the greatest common divisor of all frequencies in the circuit.

    Andrew 

  • in reply to Andrew Beckett

    Yes, the repeating period is the same. 

    The fact that there are longer high-levels every 4th or 8th edge will not affect the PSS steady state - thats what I read from your answer.

  • in reply to HoWei

    One more thing that puzzles me, is that in one testbench I get "Jc" and "Jcc" as results in the direct plot menu, but in another testbench I do not see this.

    The PNOISE setup is (apparently) the same for both:

    Noise Type: timeaverage ALL(AM,PM,USB,LSB)

    Any idea why ?

  • in reply to HoWei

    Quick answer on this - it's probably because one is driven and one is autonomous. If it's driven, you should use sampled/jitter mode.

    I don't have the bandwidth to go through your other updates, sorry - especially as you also have a support case open (but mainly because I just don't have time before I head for vacation).

    Andrew.

  • in reply to Andrew Beckett

    Hi Andrew,

    that might be the difference indeed - thanks.

    No issue if you don't find any time - I use this case also for my own (and for others) documentation.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.