PLL + PSS + PNOISE convergence

Great, the divider circuit now converges in PSS with different settings. with a clock input as a driven circuit.

Next I want to put a VCO at the input of the divider. The VCO (~480MHz) will operate close to a multiple integer (N=90) of the beat-freq=16/3MHz=5.333MHz.

As the VCO is a autonomous circuit, I need to define proper osc-nodes +/-, so

1. Where shall I select the osc-nodes - at the ring-vco output (480MHz) or at the divider-output (16MHz) or at the divider internal node with lowest freqeuncy (5.333MHz) ?

2. Will the PSS adjust its harmonics and beat-frequency to the VCO steady state frequency (e.g. 475,37546MHz) and converge with this frequency ?

And a question related to PNOISE:

When selecting the harmonic for the Pnoise result (relative offset phase-noise in dBc/Hz) - is the 1st harmonic the beat-frequency (~5.333MHz) or is it the VCO oscillation frequency (~480MHz) ?

Bthw. finally Cadence support contacted me today about my opened ticket - thats great !

Dear HoWei,

HoWei said:

1. Where shall I select the osc-nodes - at the ring-vco output (480MHz) or at the divider-output (16MHz) or at the divider internal node with lowest freqeuncy (5.333MHz) ?

I am not sure if you happened to examine either of the following very helpful application notes written to provide guidance on the proper use of pss settings in the presence of dividers:

support.cadence.com/.../ArticleAttachmentPortal

and

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nTyUEAU&pageName=ArticleContent

Both recommend, as makes sense, utilizing the lowest frequency (common) as the basis for the pss analysis as it requires there be an integral number of periods of all periodic waveforms to converge.

HoWei said:

2. Will the PSS adjust its harmonics and beat-frequency to the VCO steady state frequency (e.g. 475,37546MHz) and converge with this frequency ?

Yes.

HoWei said:

When selecting the harmonic for the Pnoise result (relative offset phase-noise in dBc/Hz) - is the 1st harmonic the beat-frequency (~5.333MHz) or is it the VCO oscillation frequency (~480MHz) ?

Since you are specifying the oscillation frequency as the minimum common periodic frequency, the harmonic in the pss analysis referred to as 1 is the lowest common frequency - or I believe 5.33 MHz in your specific case.

I hope this is useful to you HoWei.

Shawn

Dear HoWei,

HoWei said:

1. Where shall I select the osc-nodes - at the ring-vco output (480MHz) or at the divider-output (16MHz) or at the divider internal node with lowest freqeuncy (5.333MHz) ?

I am not sure if you happened to examine either of the following very helpful application notes written to provide guidance on the proper use of pss settings in the presence of dividers:

support.cadence.com/.../ArticleAttachmentPortal

and

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nTyUEAU&pageName=ArticleContent

Both recommend, as makes sense, utilizing the lowest frequency (common) as the basis for the pss analysis as it requires there be an integral number of periods of all periodic waveforms to converge.

HoWei said:

2. Will the PSS adjust its harmonics and beat-frequency to the VCO steady state frequency (e.g. 475,37546MHz) and converge with this frequency ?

Yes.

HoWei said:

When selecting the harmonic for the Pnoise result (relative offset phase-noise in dBc/Hz) - is the 1st harmonic the beat-frequency (~5.333MHz) or is it the VCO oscillation frequency (~480MHz) ?

Since you are specifying the oscillation frequency as the minimum common periodic frequency, the harmonic in the pss analysis referred to as 1 is the lowest common frequency - or I believe 5.33 MHz in your specific case.

I hope this is useful to you HoWei.

Shawn

i Shawn,

yes I read all of them - and much more during the last days. But I still do not have the feeling I have enough knowlegde to ensure I have the correct settings.

Most of the points I am asking myself are discussed on a side-note in a forum discussion - as recommendations.

About the 2 upper questions, I agree to your answers, but I think I asked something different. I try to ask more precisely:

1. Here I am asking which node in the schematic I should select as the osc-node for the autonomous circuit: The oscillator output (480MHz) or the node with the lowest frequency (5.333MHz). I understand that the beat-freq=5.333MHz (lowest in curcuit) - but which node shall I select as osc-node ?

Normally I would think of using a node inside the VCO, but it is not the node with the lowest frequency. I read somewhere to use the node with the lowest frequency. I did both - no success yet.

2. You are saying to specifiy the oscillator frequency as the minimum common periodic frequency - but that statement is contrary to itself, because the lowest frequency is in the divider (5.333MHz) and not in the VCO.  Since the beat-freq is selected to 5.333MHz, this will be the 1st harmonic, correct ?    To observe the phasenoise at 480MHz, I need to set the 90th harmonic in the Pnoise simulation, right ?

So far I am able to simulate the frequency divider by 15 as driven circuit.

Adding the VCO before divider and simulating as autonomous circuit fails. As each simulations takes >3h until it fails, I am loosing a lot of time every day without success.

Maybe PSS is not the right tool for doing this simulations, or I just have to find the proper settings - I do not know.

I am in contact with Cadence support as well.

Next thing I try is to close the PLL (with PFD and CP) and simulate as driven circuit again.

Any suggestion is very much appreciated.

Dear Howei,

A couple of comments to your comments if I may...

HoWei said:

1. Here I am asking which node in the schematic I should select as the osc-node for the autonomous circuit: The oscillator output (480MHz) or the node with the lowest frequency (5.333MHz). I understand that the beat-freq=5.333MHz (lowest in curcuit) - but which node shall I select as osc-node ?

The first link I suggested you take a look at has the explicit statement:

"If simulating an oscillator, choose the osc node to be at the output of the lowest frequency divider.  Set pss estimated frequency to the lowest divided down frequency in the circuit."

Did you happen to read this when you looked over this document - or maybe I am misunderstanding your quoted question above...did I? It definitely suggests you set the osc-node as the divided VCO output and NOT the VCO output as well as setting the expected osc frequency as the divided frequency and not the VCO frequency.

HoWei said:

2. You are saying to specifiy the oscillator frequency as the minimum common periodic frequency - but that statement is contrary to itself, because the lowest frequency is in the divider (5.333MHz) and not in the VCO.  Since the beat-freq is selected to 5.333MHz, this will be the 1st harmonic, correct ?    To observe the phasenoise at 480MHz, I need to set the 90th harmonic in the Pnoise simulation, right ?

Based on the comment above from the link I provided, your osc nodes should be set o 5.33+ MHz with the expected estimated VCO frequency set to this value. I would suggest you leave the harmonic set to 1 to compute the phase noise (if you can make pss converge) and just scale the resulting pnoise by 20*log (ratio of VCO frequency/5.33+ MHz). This will provide the phase noise relative to your VCO frequency. Further, since you are performing the pss simulation relative to 5.33+ MHz, you need to set the maximum integration step to a value much less than your VCO period - and not rely on the default integration time step. In your case, I would suggest setting it to, for example, 1/25 or 1/100 of the VCO period of 1/480MHz.

Please also make sure that your tstab value is set to a value where both the VCO frequency and the divided output frequency have reached their steady-state values or close to them. Note that if your time steps are too coarse, one reason pss may not converge is that it does not see exactly an integral number of VCO periods in your 5.33+ MHz divided output (i.e, the "quantization noise" due to your simulator time steps is too coarse to show an integral ratio of the two frequencies. Hence, it is even more important to assure there are sufficient time steps over each VCO (480 MHz) period. Does this make sense?

HoWei said:

As Shawn mentioned in the linked discussion above, there might be a way to start PSS with transient simulation results in steady state.

Is this doable ?

Andrew Beckett said:

No, PSS can't reuse transient results. You can use the save and restart with PSS, but the checkpoint needs to have been saved by the same analysis (PSS) - so you could run a stab, use the save* options to save one or more checkpoints, and restart from that. You just can't mix analyses.

Andrew

Andrew is absolutely correct (as usual). However, when I run a pss simulation that requires any significant time to run its tstab portion, I do save the checkpoint files periodically (usually at intervals of tstab/4 or so and then use the last checkpoint file if I need to re-run the pss portion).. If the pss simulation fails to converge and I want to re-run it with different settings, I simply load the checkpoint file and most all of the tstab portion of the simulation is not required and the simulation quickly starts the pss portion of the simulation.

I put together some instructions as a text file many years ago and also include a 202o On-line support article that detail how to include the checkpoint file in an Assembler/Explorer corners setup in case either is of any help to you.

HoWei said:

I am in contact with Cadence support as well.

Great. I am sure they will be more helpful than I can be!

Shawn

Creating a Saved State FIle during a Transient Simulation

SPectre can create a state file of a circuit periodically during a transient simulation. This file can be used to restart the simulation at some later time after the transient simulation is finished. Alternately, if the simulation terminates unexpectedly, the simulation can be restarted from the last saved state file.

Spectre used to support saving a "checkpoint" file, but I cannot find this option in version 6.1.1.436 of Spectre. However, the manual suggests that simulation recovery is far more robust when saving the state file in lieu of the checkpoint file.

When using ocean, one syntax for including a specific file to save the operating state is as follows:

TSTOP = 300e-09
sprintf( state_file "vcostate.srf")

analysis('tran ?stop TSTOP ?errpreset "conservative"  ?maxstep maxstep  ?savetime list("50e-09"
 "100e-09" "150e-09" "200e-09" "250e-09" "300e-09") ?savefile state_file)
 
This will save the circuit state at simulation times of 50 ns, 100 ns, 150 ns,...,300 ns. Following the simulation, the netlist directory will contain a distinct file for each of the time points as shown below.

Contents of netlist directory following simulation:

amap/                   netlister.log           spectre1.ocn
artSimEnvLog            paraplot-sim-out        spectre2.ocn
control                 raw/                    spectre4.ocn
ihnl/                   runSimulation*          vcostate.srf0_50.0ns
input.ahdlSimDB/        si.env                  vcostate.srf1_100.0ns
input.scllog            spectre.dc              vcostate.srf2_150.0ns
input.scs               spectre.fc              vcostate.srf3_200.0ns
map/                    spectre.ic              vcostate.srf4_250.0ns
netlist                 spectre.inp             vcostate.srf5_300.0ns
netlistFooter           spectre.sim
netlistHeader           spectre0.ocn


Two other options are to use "saveperiod" which saves the state file at a given simulation time interval and "saveclock" which saves the simulation results at the specified realtime interval. These two options, however, overwrite the previous state file. Hence, only a single state file will be contained in the simulation netlist directory. Spectre, by default, is supposed to save the state file every 30 minutes.

Using the Saved State FIle to Re-start a SImulation
----------------------------------------------------

The syntax to re-start a transient simulation from a saved state file named "input.scs.tran.srf" is as follows:

analysis('tran TSTOP  ?errpreset "conservative" ?recover "input.scs.tran.srf" )

One danger in using the recover option is that SPectre will overwrite the existing simulation data. Hence, it is best to copy the simulation results already completed (if you need them) to a new distinct directory name prior to restarting the simulation. There is a methodology to join the two simulation results that Cadence has documented.


sml 5/6/2009

Hi Shawn,
thanks for your explanations and comments - very helpful.

I am not sure if I understood the following comment correct, so I want to clarify, if I understood correctly:

Unknown said:

HoWei said:

2. You are saying to specifiy the oscillator frequency as the minimum common periodic frequency - but that statement is contrary to itself, because the lowest frequency is in the divider (5.333MHz) and not in the VCO.  Since the beat-freq is selected to 5.333MHz, this will be the 1st harmonic, correct ?    To observe the phasenoise at 480MHz, I need to set the 90th harmonic in the Pnoise simulation, right ?

Based on the comment above from the link I provided, your osc nodes should be set o 5.33+ MHz with the expected estimated VCO frequency set to this value.

I assume you mean to set the osc-nodes to the net where the 5.333MHz are generated, right ?

With "expected estimated VCO frequency" you mean the beat-frequency, right ?   I am a little confused about the wording, because for VCO-frequency, I refer to the 480MHz VCO-output frequency.

What I am really missing is a definitive summary/tutorial for PSS+PNOISE simulation (and Cadence support is not reacting very fast these days on my cases :-(  ), therefore I will put together what I have learned:

1. Simulating an autonomous circuit (free-running osc + divider), select the osc-node to be at the net with the lowest freqeuncy - check the divider internal frequencies, which can be much lower. Disable "Calculate (ic) automatically"
2. Simulating an driven circuit (clock-source+PLL) do not select any oscillator node and disable the oscillator setup
3. The beat-frequency is always the lowest freqeuncy (largest periode) in the circuit
4. The beat-frequency is the 1st harmonic in the simulation results - important for phasenoise harmonic selection
5. Set the integration steps to 1/25 or 1/100 of the shortest period (e.g. VCO) - if your time steps are too coarse, one reason pss may not converge is that it does not see exactly an integral number of VCO periods with lowest periode (e.g. divided output) - i.e, the "quantization noise" due to your simulator time steps is too coarse to show an integral ratio of the two frequencies 
6. The number of harmonics chosen for the nonlinear signal should be at least 5X the divide ratio of the highest / lowest frequency (alternately, you can set maxacfreq)
7. Enable "detect steady state"
8. Make sure that your tstab value is set to a value where both the highest frequency and the lowest frequency have reached their steady-state values or close to them - at least 5x the lowest divided freqeuncy. Note that if your time steps are too coarse, one reason pss may not converge is that it does not see exactly an integral number of VCO periods in your divided output period (i.e, the "quantization noise" due to your simulator time steps is too coarse to show an integral ratio of the two frequencies

Dear HoWei,

HoWei said:

I assume you mean to set the osc-nodes to the net where the 5.333MHz are generated, right ?

With "expected estimated VCO frequency" you mean the beat-frequency, right ?   I am a little confused about the wording, because for VCO-frequency, I refer to the 480MHz VCO-output frequency.

Yes, to your first question and yes to your second question. I've attached an annotated pss GUI as Figure1 that I hope helps HoWei.

Shawn

Figure 1