Library charecterization without post-layout netlists

Dear iamKarthikBK,

iamKarthikBK said:

Is there a way by which I can characterize the cells without a post layout netlist?

I am not sure what your prime objective is,but you can certainly perform a pre-layout (i.e., schematic based) netlist characterization of your cells. As to a post-layout characterization, the only insight I might provide is to characterize your cells from a set of "modified" schematics with added parasitic component estimates (such as added trace resistances and capacitances). In the cases where I have done similar analyses where the exact parasitic element values are known, is to vary the added parasitic resistor/capacitors either parametrically or independently to study the parameters you are trying to establish for the cells sensitivity to their values.

For example, for a simple CMOS inverter, you might include an rds value for each device to the positive and negative supply and vary its value between 1 ohm and 1000 ohm logarithmically (1, 10, 100, 1K) and examine its impact on, for example, output transition times. A similar process might be followed for gate resistance. Parasitic capacitances might be varied on a linear basis (1fF, 5 fF, 10 fF, 20 fF, etc.) and studied.

In this fashion, you might choose the parasitic elements to include in your schematic based netlist that appear to have significant impact on the parameters you are interested in characterizing. By adding your personal insight into their values (using sheet resistances, estimated trace topologies and dielectric capacitances for your process), you can assign a value to each parasitic element. Of course, the resulting netlist is not a replacement for an extracted view based netlist, but might provide a means to more robustly estimate the post-layout based performance than using only a Virtuoso schematic based netlist.

iamKarthikBK said:

Otherwise, is there a cloud-based service which I can use for this particular project?

I am not sure what you mean by this statement in the context of your question about characterizing cells without layout based parasitics. Sorry!

Shawn

Dear iamKarthikBK,

iamKarthikBK said:

Is there a way by which I can characterize the cells without a post layout netlist?

I am not sure what your prime objective is,but you can certainly perform a pre-layout (i.e., schematic based) netlist characterization of your cells. As to a post-layout characterization, the only insight I might provide is to characterize your cells from a set of "modified" schematics with added parasitic component estimates (such as added trace resistances and capacitances). In the cases where I have done similar analyses where the exact parasitic element values are known, is to vary the added parasitic resistor/capacitors either parametrically or independently to study the parameters you are trying to establish for the cells sensitivity to their values.

For example, for a simple CMOS inverter, you might include an rds value for each device to the positive and negative supply and vary its value between 1 ohm and 1000 ohm logarithmically (1, 10, 100, 1K) and examine its impact on, for example, output transition times. A similar process might be followed for gate resistance. Parasitic capacitances might be varied on a linear basis (1fF, 5 fF, 10 fF, 20 fF, etc.) and studied.

In this fashion, you might choose the parasitic elements to include in your schematic based netlist that appear to have significant impact on the parameters you are interested in characterizing. By adding your personal insight into their values (using sheet resistances, estimated trace topologies and dielectric capacitances for your process), you can assign a value to each parasitic element. Of course, the resulting netlist is not a replacement for an extracted view based netlist, but might provide a means to more robustly estimate the post-layout based performance than using only a Virtuoso schematic based netlist.

iamKarthikBK said:

Otherwise, is there a cloud-based service which I can use for this particular project?

I am not sure what you mean by this statement in the context of your question about characterizing cells without layout based parasitics. Sorry!

Shawn

Hi,

If your question is about Liberate characterization, the netlist don't not have to be a post-layout one. However, the impact of parasitics will not be included in your liberty file. Sometimes, people use this to do pipe cleaning for large IO cells. you can create a spectre netlist from ADE.

I am not sure how your question on cloud-based service is related. Cadence does offer cloud-based service for liberate characterization. It is normally used for very large scale characterization, eg. Thousands of cells over many corners. By accessing hundreds or thousands of CPUs, the job can be done in a short time. This may not be your choice.

Guangjun

Hi,

If your question is about Liberate characterization, the netlist don't not have to be a post-layout one. However, the impact of parasitics will not be included in your liberty file. Sometimes, people use this to do pipe cleaning for large IO cells. you can create a spectre netlist from ADE.

I am not sure how your question on cloud-based service is related. Cadence does offer cloud-based service for liberate characterization. It is normally used for very large scale characterization, eg. Thousands of cells over many corners. By accessing hundreds or thousands of CPUs, the job can be done in a short time. This may not be your choice.

Guangjun

Hi,

If your question is about Liberate characterization, the netlist don't not have to be a post-layout one. However, the impact of parasitics will not be included in your liberty file. Sometimes, people use this to do pipe cleaning for large IO cells. you can create a spectre netlist from ADE.

I am not sure how your question on cloud-based service is related. Cadence does offer cloud-based service for liberate characterization. It is normally used for very large scale characterization, eg. Thousands of cells over many corners. By accessing hundreds or thousands of CPUs, the job can be done in a short time. This may not be your choice.

Guangjun

Guangjun Cao I will not be able to perform layout verification i.e. LVS and DRC, and extraction of a post-layout netlist since the Mentor calibre licenses at my university has expired. They will take time to get them renewed. The PDK i'm using is UMC28 HPC which doesn't support assura for verification. I do have access to PVS but UMC requires a TO commitment in order for them to generate the rule decks for me.

I want to perform library charecterization using pre-layout netlists. this will not have parasitics and i am completely fine with it for now, until the Calibre licenses at my university get renewed.
How do I generate pre-layout netlists that can be used with Liberate?

I tried doing this: ADE L ~> Simulation ~> Netlist ~> create but this way, liberate tells me there are empty subcircuits.

How am I supposed to create pre-layout netlists that I can use with Liberate for library charecterization? 

About the cloud subquestion, I wanted to know if I could use the tools on the cloud, but it seems like it's only for very large workloads.
Thanks that part of the question is answered.

Hi,

Does your netlist have subckt and ends statements for the cells you want to characterize? you also need to remove any other statements/commands outside of the subckt block.

Empty subcircuits can also be a result of undefined leafcells, which should be flagged in the logfile as warnings related to leaf cells.

Guangjun  

// Generated for: spectre
// Generated on: Aug 18 14:35:59 2021
// Design library name: lowpower28
// Design cell name: ADDFHX1
// Design view name: schematic
simulator lang=spectre
global 0
include "/home/VLSI_ANALOG/UMCLib/pdk/UMC/28/_G-01-LOGIC_MIXED_MODE28N-HPC/Designkits/Cadence_IC6/G-9FD-LOGIC_MIXED_MODE28N-HPC_UM028FDKHCC0000OA-FDK-Ver.A14_PB/UM028FDKHCC0000OA_A14_DESIGNKIT/UM028FDKHCC0000OA_A14_PB/umc28hpc/../Models/Spectre/l28hpc_mm_v1201.lib.scs"
section=tt
include "/home/VLSI_ANALOG/UMCLib/pdk/UMC/28/_G-01-LOGIC_MIXED_MODE28N-HPC/Designkits/Cadence_IC6/G-9FD-LOGIC_MIXED_MODE28N-HPC_UM028FDKHCC0000OA-FDK-Ver.A14_PB/UM028FDKHCC0000OA_A14_DESIGNKIT/UM028FDKHCC0000OA_A14_PB/umc28hpc/../Models/Spectre/l28hpc_rf_v017.lib.scs"
section=tt

// Library name: lowpower28
// Cell name: ADDFHX1
// View name: schematic
PM13 (net274 CI net278 VDD) p_p9_hpculvt m=1 mf=1 w=3u l=30n nf=1 ad=225f \
        as=225f pd=6.15u ps=6.15u sa=75n sb=75n sd=0 sca=5.01945 \
        scb=2.87125m scc=522.353u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
PM10 (S net274 VDD VDD) p_p9_hpculvt m=1 mf=1 w=1.08u l=30n nf=1 ad=81f \
        as=81f pd=2.31u ps=2.31u sa=75n sb=75n sd=0 sca=13.4363 \
        scb=7.97447m scc=1.45098m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
PM9 (CO net277 VDD VDD) p_p9_hpculvt m=1 mf=1 w=1.08u l=30n nf=1 ad=81f \
        as=81f pd=2.31u ps=2.31u sa=75n sb=75n sd=0 sca=13.4363 \
        scb=7.97447m scc=1.45098m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
PM12 (net278 B net273 VDD) p_p9_hpculvt m=1 mf=1 w=3u l=30n nf=1 ad=225f \
        as=225f pd=6.15u ps=6.15u sa=75n sb=75n sd=0 sca=5.01945 \
        scb=2.87125m scc=522.353u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
PM11 (net273 A VDD VDD) p_p9_hpculvt m=1 mf=1 w=3u l=30n nf=1 ad=225f \
        as=225f pd=6.15u ps=6.15u sa=75n sb=75n sd=0 sca=5.01945 \
        scb=2.87125m scc=522.353u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
PM6 (net272 B VDD VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
        as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
        scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
PM5 (net272 A VDD VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
        as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
        scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
PM8 (net274 net277 net272 VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 \
        ad=162f as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
        scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
PM4 (net277 CI net271 VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 \
        ad=162f as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
        scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
PM3 (net271 B VDD VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
        as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
        scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
PM2 (net271 A VDD VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
        as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
        scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
PM7 (net272 CI VDD VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
        as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
        scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
PM1 (net277 B net279 VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
        as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
        scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
PM0 (net279 A VDD VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
        as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
        scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
NM1 (net280 A GND GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
        as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
        scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
NM8 (net275 CI GND GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
        as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
        scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
NM0 (net277 B net280 GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
        as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
        scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
NM7 (net274 net277 net275 GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 \
        ad=15f as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 \
        scb=30.1749m scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
NM6 (net275 B GND GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
        as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
        scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
NM5 (net275 A GND GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
        as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
        scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
NM2 (net270 A GND GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
        as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
        scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
NM4 (net270 B GND GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
        as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
        scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
NM3 (net277 CI net270 GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
        as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
        scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
NM9 (S net274 GND GND) n_p9_hpculvt m=1 mf=1 w=100n l=30n nf=1 ad=7.5f \
        as=7.5f pd=350n ps=350n sa=75n sb=75n sd=0 sca=93.2401 \
        scb=35.2443m scc=11.7056m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
NM12 (net276 B net062 GND) n_p9_hpculvt m=1 mf=1 w=300n l=30n nf=1 \
        ad=22.5f as=22.5f pd=750n ps=750n sa=75n sb=75n sd=0 sca=42.1496 \
        scb=24.6839m scc=5.1768m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
NM13 (net274 CI net276 GND) n_p9_hpculvt m=1 mf=1 w=300n l=30n nf=1 \
        ad=22.5f as=22.5f pd=750n ps=750n sa=75n sb=75n sd=0 sca=42.1496 \
        scb=24.6839m scc=5.1768m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
NM11 (net062 A GND GND) n_p9_hpculvt m=1 mf=1 w=300n l=30n nf=1 ad=22.5f \
        as=22.5f pd=750n ps=750n sa=75n sb=75n sd=0 sca=42.1496 \
        scb=24.6839m scc=5.1768m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
NM10 (CO net277 GND GND) n_p9_hpculvt m=1 mf=1 w=100n l=30n nf=1 ad=7.5f \
        as=7.5f pd=350n ps=350n sa=75n sb=75n sd=0 sca=93.2401 \
        scb=35.2443m scc=11.7056m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
        rgate_flag=1
simulatorOptions options psfversion="1.4.0" reltol=1e-3 vabstol=1e-6 \
    iabstol=1e-12 temp=27 tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 \
    maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 \
    sensfile="../psf/sens.output" checklimitdest=psf
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub

This is my netlist that ADE L gives. How am I supposed to edit this?
Thanks

Try this,

// remove all lines above

subckt <your cell_name>  <all pins>

PM13 (net274 CI net278 VDD) ......

......

NM10 (CO net277 GND GND) ......

ends <your cell_name> 

//// remove all lines below

Guangjun