Library charecterization without post-layout netlists

Dear iamKarthikBK,

iamKarthikBK said:

Is there a way by which I can characterize the cells without a post layout netlist?

I am not sure what your prime objective is,but you can certainly perform a pre-layout (i.e., schematic based) netlist characterization of your cells. As to a post-layout characterization, the only insight I might provide is to characterize your cells from a set of "modified" schematics with added parasitic component estimates (such as added trace resistances and capacitances). In the cases where I have done similar analyses where the exact parasitic element values are known, is to vary the added parasitic resistor/capacitors either parametrically or independently to study the parameters you are trying to establish for the cells sensitivity to their values.

For example, for a simple CMOS inverter, you might include an rds value for each device to the positive and negative supply and vary its value between 1 ohm and 1000 ohm logarithmically (1, 10, 100, 1K) and examine its impact on, for example, output transition times. A similar process might be followed for gate resistance. Parasitic capacitances might be varied on a linear basis (1fF, 5 fF, 10 fF, 20 fF, etc.) and studied.

In this fashion, you might choose the parasitic elements to include in your schematic based netlist that appear to have significant impact on the parameters you are interested in characterizing. By adding your personal insight into their values (using sheet resistances, estimated trace topologies and dielectric capacitances for your process), you can assign a value to each parasitic element. Of course, the resulting netlist is not a replacement for an extracted view based netlist, but might provide a means to more robustly estimate the post-layout based performance than using only a Virtuoso schematic based netlist.

iamKarthikBK said:

Otherwise, is there a cloud-based service which I can use for this particular project?

I am not sure what you mean by this statement in the context of your question about characterizing cells without layout based parasitics. Sorry!

Shawn

Dear iamKarthikBK,

iamKarthikBK said:

Is there a way by which I can characterize the cells without a post layout netlist?

I am not sure what your prime objective is,but you can certainly perform a pre-layout (i.e., schematic based) netlist characterization of your cells. As to a post-layout characterization, the only insight I might provide is to characterize your cells from a set of "modified" schematics with added parasitic component estimates (such as added trace resistances and capacitances). In the cases where I have done similar analyses where the exact parasitic element values are known, is to vary the added parasitic resistor/capacitors either parametrically or independently to study the parameters you are trying to establish for the cells sensitivity to their values.

For example, for a simple CMOS inverter, you might include an rds value for each device to the positive and negative supply and vary its value between 1 ohm and 1000 ohm logarithmically (1, 10, 100, 1K) and examine its impact on, for example, output transition times. A similar process might be followed for gate resistance. Parasitic capacitances might be varied on a linear basis (1fF, 5 fF, 10 fF, 20 fF, etc.) and studied.

In this fashion, you might choose the parasitic elements to include in your schematic based netlist that appear to have significant impact on the parameters you are interested in characterizing. By adding your personal insight into their values (using sheet resistances, estimated trace topologies and dielectric capacitances for your process), you can assign a value to each parasitic element. Of course, the resulting netlist is not a replacement for an extracted view based netlist, but might provide a means to more robustly estimate the post-layout based performance than using only a Virtuoso schematic based netlist.

iamKarthikBK said:

Otherwise, is there a cloud-based service which I can use for this particular project?

I am not sure what you mean by this statement in the context of your question about characterizing cells without layout based parasitics. Sorry!

Shawn

Dear iamKarthikBK,

iamKarthikBK said:

Is there a way by which I can characterize the cells without a post layout netlist?

I am not sure what your prime objective is,but you can certainly perform a pre-layout (i.e., schematic based) netlist characterization of your cells. As to a post-layout characterization, the only insight I might provide is to characterize your cells from a set of "modified" schematics with added parasitic component estimates (such as added trace resistances and capacitances). In the cases where I have done similar analyses where the exact parasitic element values are known, is to vary the added parasitic resistor/capacitors either parametrically or independently to study the parameters you are trying to establish for the cells sensitivity to their values.

For example, for a simple CMOS inverter, you might include an rds value for each device to the positive and negative supply and vary its value between 1 ohm and 1000 ohm logarithmically (1, 10, 100, 1K) and examine its impact on, for example, output transition times. A similar process might be followed for gate resistance. Parasitic capacitances might be varied on a linear basis (1fF, 5 fF, 10 fF, 20 fF, etc.) and studied.

In this fashion, you might choose the parasitic elements to include in your schematic based netlist that appear to have significant impact on the parameters you are interested in characterizing. By adding your personal insight into their values (using sheet resistances, estimated trace topologies and dielectric capacitances for your process), you can assign a value to each parasitic element. Of course, the resulting netlist is not a replacement for an extracted view based netlist, but might provide a means to more robustly estimate the post-layout based performance than using only a Virtuoso schematic based netlist.

iamKarthikBK said:

Otherwise, is there a cloud-based service which I can use for this particular project?

I am not sure what you mean by this statement in the context of your question about characterizing cells without layout based parasitics. Sorry!

Shawn