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Library charecterization without post-layout netlists

iamKarthikBK

Hello.

I want to characterize cells created in Virtuoso into a standard cell library. I do not have access to the LVS and extraction tool that is supported by the PDK.
(The foundry's golden tool is Calibre/XRC and they do not generate PVS decks without a tapeout commitment. I only have access to assura and PVS.)

Is there a way by which I can characterize the cells without a post layout netlist?
Otherwise, is there a cloud-based service which I can use for this particular project?

Thanks in advance for taking time to answer this question :)

Parents

  • Hi,

    If your question is about Liberate characterization, the netlist don't not have to be a post-layout one. However, the impact of parasitics will not be included in your liberty file. Sometimes, people use this to do pipe cleaning for large IO cells. you can create a spectre netlist from ADE.

    I am not sure how your question on cloud-based service is related. Cadence does offer cloud-based service for liberate characterization. It is normally used for very large scale characterization, eg. Thousands of cells over many corners. By accessing hundreds or thousands of CPUs, the job can be done in a short time. This may not be your choice.

    Guangjun

  • in reply to Guangjun Cao

    I will not be able to perform layout verification i.e. LVS and DRC, and extraction of a post-layout netlist since the Mentor calibre licenses at my university has expired. They will take time to get them renewed. The PDK i'm using is UMC28 HPC which doesn't support assura for verification. I do have access to PVS but UMC requires a TO commitment in order for them to generate the rule decks for me.

    I want to perform library charecterization using pre-layout netlists. this will not have parasitics and i am completely fine with it for now, until the Calibre licenses at my university get renewed.
    How do I generate pre-layout netlists that can be used with Liberate?

    I tried doing this: ADE L ~> Simulation ~> Netlist ~> create but this way, liberate tells me there are empty subcircuits.

    How am I supposed to create pre-layout netlists that I can use with Liberate for library charecterization? 

  • in reply to iamKarthikBK

    Hi,

    Does your netlist have subckt and ends statements for the cells you want to characterize? you also need to remove any other statements/commands outside of the subckt block.

    Empty subcircuits can also be a result of undefined leafcells, which should be flagged in the logfile as warnings related to leaf cells.

    Guangjun  

  • in reply to Guangjun Cao

    // Generated for: spectre
    // Generated on: Aug 18 14:35:59 2021
    // Design library name: lowpower28
    // Design cell name: ADDFHX1
    // Design view name: schematic
    simulator lang=spectre
    global 0
    include "/home/VLSI_ANALOG/UMCLib/pdk/UMC/28/_G-01-LOGIC_MIXED_MODE28N-HPC/Designkits/Cadence_IC6/G-9FD-LOGIC_MIXED_MODE28N-HPC_UM028FDKHCC0000OA-FDK-Ver.A14_PB/UM028FDKHCC0000OA_A14_DESIGNKIT/UM028FDKHCC0000OA_A14_PB/umc28hpc/../Models/Spectre/l28hpc_mm_v1201.lib.scs"
    section=tt
    include "/home/VLSI_ANALOG/UMCLib/pdk/UMC/28/_G-01-LOGIC_MIXED_MODE28N-HPC/Designkits/Cadence_IC6/G-9FD-LOGIC_MIXED_MODE28N-HPC_UM028FDKHCC0000OA-FDK-Ver.A14_PB/UM028FDKHCC0000OA_A14_DESIGNKIT/UM028FDKHCC0000OA_A14_PB/umc28hpc/../Models/Spectre/l28hpc_rf_v017.lib.scs"
    section=tt

    // Library name: lowpower28
    // Cell name: ADDFHX1
    // View name: schematic
    PM13 (net274 CI net278 VDD) p_p9_hpculvt m=1 mf=1 w=3u l=30n nf=1 ad=225f \
            as=225f pd=6.15u ps=6.15u sa=75n sb=75n sd=0 sca=5.01945 \
            scb=2.87125m scc=522.353u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM10 (S net274 VDD VDD) p_p9_hpculvt m=1 mf=1 w=1.08u l=30n nf=1 ad=81f \
            as=81f pd=2.31u ps=2.31u sa=75n sb=75n sd=0 sca=13.4363 \
            scb=7.97447m scc=1.45098m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM9 (CO net277 VDD VDD) p_p9_hpculvt m=1 mf=1 w=1.08u l=30n nf=1 ad=81f \
            as=81f pd=2.31u ps=2.31u sa=75n sb=75n sd=0 sca=13.4363 \
            scb=7.97447m scc=1.45098m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM12 (net278 B net273 VDD) p_p9_hpculvt m=1 mf=1 w=3u l=30n nf=1 ad=225f \
            as=225f pd=6.15u ps=6.15u sa=75n sb=75n sd=0 sca=5.01945 \
            scb=2.87125m scc=522.353u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM11 (net273 A VDD VDD) p_p9_hpculvt m=1 mf=1 w=3u l=30n nf=1 ad=225f \
            as=225f pd=6.15u ps=6.15u sa=75n sb=75n sd=0 sca=5.01945 \
            scb=2.87125m scc=522.353u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM6 (net272 B VDD VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
            as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
            scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM5 (net272 A VDD VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
            as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
            scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM8 (net274 net277 net272 VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 \
            ad=162f as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
            scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM4 (net277 CI net271 VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 \
            ad=162f as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
            scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM3 (net271 B VDD VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
            as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
            scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM2 (net271 A VDD VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
            as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
            scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM7 (net272 CI VDD VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
            as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
            scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM1 (net277 B net279 VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
            as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
            scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM0 (net279 A VDD VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
            as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
            scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    NM1 (net280 A GND GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
            as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
            scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
    NM8 (net275 CI GND GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
            as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
            scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
    NM0 (net277 B net280 GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
            as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
            scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
    NM7 (net274 net277 net275 GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 \
            ad=15f as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 \
            scb=30.1749m scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    NM6 (net275 B GND GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
            as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
            scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
    NM5 (net275 A GND GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
            as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
            scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
    NM2 (net270 A GND GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
            as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
            scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
    NM4 (net270 B GND GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
            as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
            scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
    NM3 (net277 CI net270 GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
            as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
            scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
    NM9 (S net274 GND GND) n_p9_hpculvt m=1 mf=1 w=100n l=30n nf=1 ad=7.5f \
            as=7.5f pd=350n ps=350n sa=75n sb=75n sd=0 sca=93.2401 \
            scb=35.2443m scc=11.7056m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    NM12 (net276 B net062 GND) n_p9_hpculvt m=1 mf=1 w=300n l=30n nf=1 \
            ad=22.5f as=22.5f pd=750n ps=750n sa=75n sb=75n sd=0 sca=42.1496 \
            scb=24.6839m scc=5.1768m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    NM13 (net274 CI net276 GND) n_p9_hpculvt m=1 mf=1 w=300n l=30n nf=1 \
            ad=22.5f as=22.5f pd=750n ps=750n sa=75n sb=75n sd=0 sca=42.1496 \
            scb=24.6839m scc=5.1768m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    NM11 (net062 A GND GND) n_p9_hpculvt m=1 mf=1 w=300n l=30n nf=1 ad=22.5f \
            as=22.5f pd=750n ps=750n sa=75n sb=75n sd=0 sca=42.1496 \
            scb=24.6839m scc=5.1768m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    NM10 (CO net277 GND GND) n_p9_hpculvt m=1 mf=1 w=100n l=30n nf=1 ad=7.5f \
            as=7.5f pd=350n ps=350n sa=75n sb=75n sd=0 sca=93.2401 \
            scb=35.2443m scc=11.7056m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    simulatorOptions options psfversion="1.4.0" reltol=1e-3 vabstol=1e-6 \
        iabstol=1e-12 temp=27 tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 \
        maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 \
        sensfile="../psf/sens.output" checklimitdest=psf
    modelParameter info what=models where=rawfile
    element info what=inst where=rawfile
    outputParameter info what=output where=rawfile
    designParamVals info what=parameters where=rawfile
    primitives info what=primitives where=rawfile
    subckts info what=subckts where=rawfile
    saveOptions options save=allpub

    This is my netlist that ADE L gives. How am I supposed to edit this?
    Thanks

  • in reply to iamKarthikBK

    Try this,

    // remove all lines above

    subckt <your cell_name>  <all pins>

    PM13 (net274 CI net278 VDD) ......

    ......

    NM10 (CO net277 GND GND) ......

    ends <your cell_name> 

    //// remove all lines below

    Guangjun

  • in reply to Guangjun Cao

    Here is the netlist i created: 

    subckt ADDFHX1 S CO A B CI VDD GND
    PM13 (net274 CI net278 VDD) p_p9_hpculvt m=1 mf=1 w=3u l=30n nf=1 ad=225f \
            as=225f pd=6.15u ps=6.15u sa=75n sb=75n sd=0 sca=5.01945 \
            scb=2.87125m scc=522.353u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM10 (S net274 VDD VDD) p_p9_hpculvt m=1 mf=1 w=1.08u l=30n nf=1 ad=81f \
            as=81f pd=2.31u ps=2.31u sa=75n sb=75n sd=0 sca=13.4363 \
            scb=7.97447m scc=1.45098m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM9 (CO net277 VDD VDD) p_p9_hpculvt m=1 mf=1 w=1.08u l=30n nf=1 ad=81f \
            as=81f pd=2.31u ps=2.31u sa=75n sb=75n sd=0 sca=13.4363 \
            scb=7.97447m scc=1.45098m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM12 (net278 B net273 VDD) p_p9_hpculvt m=1 mf=1 w=3u l=30n nf=1 ad=225f \
            as=225f pd=6.15u ps=6.15u sa=75n sb=75n sd=0 sca=5.01945 \
            scb=2.87125m scc=522.353u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM11 (net273 A VDD VDD) p_p9_hpculvt m=1 mf=1 w=3u l=30n nf=1 ad=225f \
            as=225f pd=6.15u ps=6.15u sa=75n sb=75n sd=0 sca=5.01945 \
            scb=2.87125m scc=522.353u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM6 (net272 B VDD VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
            as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
            scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM5 (net272 A VDD VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
            as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
            scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM8 (net274 net277 net272 VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 \
            ad=162f as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
            scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM4 (net277 CI net271 VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 \
            ad=162f as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
            scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM3 (net271 B VDD VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
            as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
            scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM2 (net271 A VDD VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
            as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
            scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM7 (net272 CI VDD VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
            as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
            scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM1 (net277 B net279 VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
            as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
            scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    PM0 (net279 A VDD VDD) p_p9_hpculvt m=1 mf=1 w=2.16u l=30n nf=1 ad=162f \
            as=162f pd=4.47u ps=4.47u sa=75n sb=75n sd=0 sca=6.91443 \
            scb=3.98785m scc=725.49u mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    NM1 (net280 A GND GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
            as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
            scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
    NM8 (net275 CI GND GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
            as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
            scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
    NM0 (net277 B net280 GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
            as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
            scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
    NM7 (net274 net277 net275 GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 \
            ad=15f as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 \
            scb=30.1749m scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    NM6 (net275 B GND GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
            as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
            scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
    NM5 (net275 A GND GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
            as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
            scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
    NM2 (net270 A GND GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
            as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
            scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
    NM4 (net270 B GND GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
            as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
            scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
    NM3 (net277 CI net270 GND) n_p9_hpculvt m=1 mf=1 w=200n l=30n nf=1 ad=15f \
            as=15f pd=550n ps=550n sa=75n sb=75n sd=0 sca=58.0552 scb=30.1749m \
            scc=7.4422m mis_flag=1 cctg_flag=1 rdscon_flag=1 rgate_flag=1
    NM9 (S net274 GND GND) n_p9_hpculvt m=1 mf=1 w=100n l=30n nf=1 ad=7.5f \
            as=7.5f pd=350n ps=350n sa=75n sb=75n sd=0 sca=93.2401 \
            scb=35.2443m scc=11.7056m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    NM12 (net276 B net062 GND) n_p9_hpculvt m=1 mf=1 w=300n l=30n nf=1 \
            ad=22.5f as=22.5f pd=750n ps=750n sa=75n sb=75n sd=0 sca=42.1496 \
            scb=24.6839m scc=5.1768m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    NM13 (net274 CI net276 GND) n_p9_hpculvt m=1 mf=1 w=300n l=30n nf=1 \
            ad=22.5f as=22.5f pd=750n ps=750n sa=75n sb=75n sd=0 sca=42.1496 \
            scb=24.6839m scc=5.1768m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    NM11 (net062 A GND GND) n_p9_hpculvt m=1 mf=1 w=300n l=30n nf=1 ad=22.5f \
            as=22.5f pd=750n ps=750n sa=75n sb=75n sd=0 sca=42.1496 \
            scb=24.6839m scc=5.1768m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    NM10 (CO net277 GND GND) n_p9_hpculvt m=1 mf=1 w=100n l=30n nf=1 ad=7.5f \
            as=7.5f pd=350n ps=350n sa=75n sb=75n sd=0 sca=93.2401 \
            scb=35.2443m scc=11.7056m mis_flag=1 cctg_flag=1 rdscon_flag=1 \
            rgate_flag=1
    ends ADDFHX1

    Here are the logs from liberate:

    [VLSI_ANALOG@cad19 liberate]$ csh
    [VLSI_ANALOG@cad19 liberate]$ source /home/installs/cshrc


    Welcome to Cadence Tools Suite

    [VLSI_ANALOG@cad19 liberate]$ liberate char.tcl
    ROOT_DIR = /home/installs/LIBERATE192
    exepath = /home/installs/LIBERATE192/tools/bin
    Host : cad19 x86_64 Linux 2.6.32-696.el6.x86_64
    LIBERATE Library Characterization Platform (x86_64)
    Release dev, compiled by vficcm on Tue Sep 10 06:33:00 PDT 2019


        ********************************************************************
        *   Copyright ©  Cadence Design Systems, Inc.  2006 - 2021.      *
        *             All rights reserved.                                 *
        *                                                                  *
        *                                                                  *
        *                                                                  *
        * This program contains confidential and trade secret information  *
        * of Cadence Design Systems, Inc. and is protected by copyright    *
        * law and international treaties.  Any reproduction, use,          *
        * distribution or disclosure of this program or any portion of it, *
        * or any attempt to obtain a human-readable version of this        *
        * program, without the express, prior written consent of           *
        * Cadence Design Systems, Inc., is strictly prohibited.            *
        *                                                                  *
        *         Cadence Design Systems, Inc.                             *
        *           2655 Seely Avenue                                      *
        *           San Jose, CA 95134,  USA                               *
        *                                                                  *
        *                                                                  *
        ********************************************************************


        Copyright notices for Open Source and Third Party Tools used by this
        software can be viewed at
    <cds_inst_dir>/doc/liberate/thirdpartyinfo/Notices.txt

    LIBERATE started on cad19 at Wed Aug 18 15:07:54 2021

    Command line arguments: 'char.tcl'.
    ALTOSHOME set to '/home/installs/LIBERATE192'.
    Server ID : T20210818150754105353S0013658
    LIBERATE parameter "slew_lower_rise" set to "0.2"
    LIBERATE parameter "slew_upper_rise" set to "0.8"
    LIBERATE parameter "slew_lower_fall" set to "0.2"
    LIBERATE parameter "slew_upper_fall" set to "0.8"
    LIBERATE parameter "measure_slew_lower_rise" set to "0.2"
    LIBERATE parameter "measure_slew_upper_rise" set to "0.8"
    LIBERATE parameter "measure_slew_lower_fall" set to "0.2"
    LIBERATE parameter "measure_slew_upper_fall" set to "0.8"
    LIBERATE parameter "min_transition" set to "6e-12"
    LIBERATE parameter "max_transition" set to "2e-07"
    LIBERATE parameter "min_output_cap" set to "1e-16"
    LIBERATE parameter "spectre_pwr" set to "0"
    LIBERATE parameter "simulator" set to "ski"
    WARNING (LIB-162): (define_cell): The pin(s): 'VDD GND' that have been
    included as input/bidi/output/clock/async/sleep pin(s) for cell:
    'addfhx1' are actually supply pins (see set_vdd/set_gnd). Either do
    not mark these as supply pins or remove them from the 'define_cell'
    command and rerun.
    LIBERATE parameter "char_library_skip_var_list" set to ""
    Start Characterizing Library at (Wed Aug 18 15:08:00 IST 2021)

    *Info* Removing all types
    *Info* Max Shared Memory Segments : 4096
    *Info* No Shared Memory Segments
    *Info* Max Semaphore Arrays : 128
    *Info* Max Message Queues : 7577
    *Info* No Message Queues
    *Info* No Zombie Processes
    WARNING (LIB-103): When using Spectre-SKI, runtime may significantly
    improve when using an extsim_model_include/define_leafcell flow.  This
    is needed to enable the Spectre modellib flow.
    ERROR (LIB-902): Failed to open file
    '/home/VLSI_ANALOG/Backup/UMC180/Designkits/Cadence_6.1/lowpower/liberate/NETLIST/ADDFHX1.sp'
    for read. Check directory/file paths and permissions and rerun.
    Peak memory usage:          336 MB
    Peak virtual memory usage:  302 MB
    Peak physical memory usage: 34 MB
    Wall time      :    0.00 hours (9.00 seconds)
    LIBERATE exited on cad19 at Wed Aug 18 15:08:02 2021

    [VLSI_ANALOG@cad19 liberate]$
    [VLSI_ANALOG@cad19 liberate]$ liberate char.tcl
    ROOT_DIR = /home/installs/LIBERATE192
    exepath = /home/installs/LIBERATE192/tools/bin
    Host : cad19 x86_64 Linux 2.6.32-696.el6.x86_64
    LIBERATE Library Characterization Platform (x86_64)
    Release dev, compiled by vficcm on Tue Sep 10 06:33:00 PDT 2019


        ********************************************************************
        *   Copyright ©  Cadence Design Systems, Inc.  2006 - 2021.      *
        *             All rights reserved.                                 *
        *                                                                  *
        *                                                                  *
        *                                                                  *
        * This program contains confidential and trade secret information  *
        * of Cadence Design Systems, Inc. and is protected by copyright    *
        * law and international treaties.  Any reproduction, use,          *
        * distribution or disclosure of this program or any portion of it, *
        * or any attempt to obtain a human-readable version of this        *
        * program, without the express, prior written consent of           *
        * Cadence Design Systems, Inc., is strictly prohibited.            *
        *                                                                  *
        *         Cadence Design Systems, Inc.                             *
        *           2655 Seely Avenue                                      *
        *           San Jose, CA 95134,  USA                               *
        *                                                                  *
        *                                                                  *
        ********************************************************************


        Copyright notices for Open Source and Third Party Tools used by this
        software can be viewed at
    <cds_inst_dir>/doc/liberate/thirdpartyinfo/Notices.txt

    LIBERATE started on cad19 at Wed Aug 18 15:08:29 2021

    Command line arguments: 'char.tcl'.
    ALTOSHOME set to '/home/installs/LIBERATE192'.
    Server ID : T20210818150829815566S0013820
    LIBERATE parameter "slew_lower_rise" set to "0.2"
    LIBERATE parameter "slew_upper_rise" set to "0.8"
    LIBERATE parameter "slew_lower_fall" set to "0.2"
    LIBERATE parameter "slew_upper_fall" set to "0.8"
    LIBERATE parameter "measure_slew_lower_rise" set to "0.2"
    LIBERATE parameter "measure_slew_upper_rise" set to "0.8"
    LIBERATE parameter "measure_slew_lower_fall" set to "0.2"
    LIBERATE parameter "measure_slew_upper_fall" set to "0.8"
    LIBERATE parameter "min_transition" set to "6e-12"
    LIBERATE parameter "max_transition" set to "2e-07"
    LIBERATE parameter "min_output_cap" set to "1e-16"
    LIBERATE parameter "spectre_pwr" set to "0"
    LIBERATE parameter "simulator" set to "ski"
    WARNING (LIB-162): (define_cell): The pin(s): 'VDD GND' that have been
    included as input/bidi/output/clock/async/sleep pin(s) for cell:
    'addfhx1' are actually supply pins (see set_vdd/set_gnd). Either do
    not mark these as supply pins or remove them from the 'define_cell'
    command and rerun.
    LIBERATE parameter "char_library_skip_var_list" set to ""
    Start Characterizing Library at (Wed Aug 18 15:08:33 IST 2021)

    *Info* Removing all types
    *Info* Max Shared Memory Segments : 4096
    *Info* No Shared Memory Segments
    *Info* Max Semaphore Arrays : 128
    *Info* Max Message Queues : 7577
    *Info* No Message Queues
    *Info* No Zombie Processes
    WARNING (LIB-103): When using Spectre-SKI, runtime may significantly
    improve when using an extsim_model_include/define_leafcell flow.  This
    is needed to enable the Spectre modellib flow.
    INFO (LIB-956): (read_spice): Reading file:
    '/home/VLSI_ANALOG/Backup/UMC180/Designkits/Cadence_6.1/lowpower/liberate/MODELS/include_tt.sp'.
    INFO (LIB-956): (read_spice): Reading file:
    '/home/VLSI_ANALOG/Backup/UMC180/Designkits/Cadence_6.1/lowpower/liberate/NETLIST/ADDFHX1.scs'.
    WARNING (LIB-933): To enable automatic leaf-cell recognition, the
    variable 'extsim_model_include' is required.
    INFO (LIB-940): The parser has identified the following leaf cells.
    Review these for missing or incorrect settings and if needed, add them
    to your Tcl script and rerun.
    INFO (LIB-906): (AUTO): define_leafcell -type diode -pin_position {0
    1} dion_1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type diode -pin_position {0
    1} dion_2p5_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type diode -pin_position {0
    1} dion_gated_ground_1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type diode -pin_position {0
    1} dion_p9_hpchvt
    INFO (LIB-906): (AUTO): define_leafcell -type diode -pin_position {0
    1} dion_p9_hpclvt
    INFO (LIB-906): (AUTO): define_leafcell -type diode -pin_position {0
    1} dion_p9_hpcrvt
    INFO (LIB-906): (AUTO): define_leafcell -type diode -pin_position {0
    1} dion_p9_hpcuhvt
    INFO (LIB-906): (AUTO): define_leafcell -type diode -pin_position {0
    1} dion_p9_hpculvt
    INFO (LIB-906): (AUTO): define_leafcell -type diode -pin_position {0
    1} diop_1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type diode -pin_position {0
    1} diop_2p5_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type diode -pin_position {0
    1} diop_gated_ground_1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type diode -pin_position {0
    1} diop_p9_hpchvt
    INFO (LIB-906): (AUTO): define_leafcell -type diode -pin_position {0
    1} diop_p9_hpclvt
    INFO (LIB-906): (AUTO): define_leafcell -type diode -pin_position {0
    1} diop_p9_hpcrvt
    INFO (LIB-906): (AUTO): define_leafcell -type diode -pin_position {0
    1} diop_p9_hpcuhvt
    INFO (LIB-906): (AUTO): define_leafcell -type diode -pin_position {0
    1} diop_p9_hpculvt
    INFO (LIB-906): (AUTO): define_leafcell -type c -pin_position {0 1 2}
    momcaps_sy_3p3_mmkf
    INFO (LIB-906): (AUTO): define_leafcell -type c -pin_position {0 1 2}
    momcaps_sy_mmkf
    INFO (LIB-906): (AUTO): define_leafcell -type c -pin_position {0 1 2 3
    4} momcaps_symesh_3p3_mmkf
    INFO (LIB-906): (AUTO): define_leafcell -type c -pin_position {0 1 2 3
    4} momcaps_symesh_mmkf
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_1p8_hpcnvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_1p8ud1p2_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_1p8ud1p5_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_1p8ud1p5_hpcnvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_2p5_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_2p5_hpcnvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_2p5od3p3_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_2p5od3p3_hpcnvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_2p5ud1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_2p5ud1p8_hpcnvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3 4 5} n_dnw_1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3 4 5} n_dnw_1p8ud1p2_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3 4 5} n_dnw_1p8ud1p5_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3 4 5} n_dnw_2p5_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3 4 5} n_dnw_2p5od3p3_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3 4 5} n_dnw_2p5ud1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3 4 5} n_dnw_p9_hpchvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3 4 5} n_dnw_p9_hpclvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3 4 5} n_dnw_p9_hpcrvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3 4 5} n_dnw_p9_hpcuhvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3 4 5} n_dnw_p9_hpculvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_esd_1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_esd_1p8ud1p2_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_esd_1p8ud1p5_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_esd_2p5_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_esd_2p5od3p3_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_esd_2p5ud1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_esd_p9_hpcrvt
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} n_p9_hpchvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_p9_hpclvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_p9_hpcrnvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_p9_hpcrvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_p9_hpcuhvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_p9_hpculvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_pdp127_hpcsphvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_pdp155_hpcsphvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_pdp240b_hpcsphvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_pdp315_hpcsphvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_pdrp240b_hpcsphvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_pesd_1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_pesd_1p8ud1p2_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_pesd_1p8ud1p5_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_pesd_2p5_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_pesd_2p5od3p3_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_pesd_2p5ud1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_pgp127_hpcsphvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_pgp155_hpcsphvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_pgp240b_hpcsphvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_pgp315_hpcsphvt
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} n_pgrp240b_hpcsphvt
    INFO (LIB-906): (AUTO): define_leafcell -type c -pin_position {0 1} ncap_p9_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} nd_ld_d5g1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1
    2 3} nd_ld_d5g2p5_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type npn -pin_position {0 1
    2} npn_v1p44x1p44_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type npn -pin_position {0 1
    2} npn_v1p8x1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type npn -pin_position {0 1
    2} npn_v2p88x2p88_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type npn -pin_position {0 1
    2} npn_v4p5x4p5_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type npn -pin_position {0 1
    2} npn_v9x9_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_1p8ud1p2_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_1p8ud1p5_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_2p5_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_2p5od3p3_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_2p5ud1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_esd_1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_esd_1p8ud1p2_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_esd_1p8ud1p5_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_esd_2p5_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_esd_2p5od3p3_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_esd_2p5ud1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_esd_p9_hpcrvt
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_lp127_hpcsphvt
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_lp155_hpcsphvt
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_lp240b_hpcsphvt
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_lp315_hpcsphvt
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_p9_hpchvt
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_p9_hpclvt
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_p9_hpcrvt
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_p9_hpcuhvt
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} p_p9_hpculvt
    INFO (LIB-906): (AUTO): define_leafcell -type c -pin_position {0 1} pcap_p9_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} pd_ld_d5g1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1
    2 3} pd_ld_d5g2p5_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pnp -pin_position {0 1
    2} pnp_v1p44x1p44_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pnp -pin_position {0 1
    2} pnp_v1p8x1p8_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pnp -pin_position {0 1
    2} pnp_v2p88x2p88_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pnp -pin_position {0 1
    2} pnp_v4p5x4p5_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type pnp -pin_position {0 1
    2} pnp_v9x9_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type r -pin_position {0 1 2} rhr_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type r -pin_position {0 1 2} rnnd_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type r -pin_position {0 1 2} rnpd_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type r -pin_position {0 1 2} rsnd_hpc
    INFO (LIB-906): (AUTO): define_leafcell -type r -pin_position {0 1 2} rspd_hpc
    INFO (LIB-907): (AUTO): define_leafcell -element -type c -pin_position
    {0 1} main_c_vp1
    INFO (LIB-907): (AUTO): define_leafcell -element -type r -pin_position
    {0 1} res2
    INFO (LIB-943): Finished reading netlist(s) at Aug 18 15:08:38.
    INFO (LIB-711): Feature 'Virtuoso_Multi_mode_Simulation' exists in the
    license pool. The parameter 'spectre_use_mmsim_token_license' will be
    set to '1'.
    INFO (LIB-1008): (char_library): This LIBERATE release was qualified
    with MMSIM version '' but newer version '19.1.0.396.isr8' was
    detected. If MMSIM-related issues are found, update to the qualified
    MMSIM version and re-run.
    *Info* (char_library) : SKI process child signal handler enabled.

    INFO (LIB-966): Using Spectre version 19.1.0.396.isr8 located at:
    /home/installs/SPECTRE191/tools/bin/spectre.
    *Info* Use temporary directory
    '/home/VLSI_ANALOG/Backup/UMC180/Designkits/Cadence_6.1/lowpower/liberate'.
    LIBERATE parameter "extsim_deck_dir" defaulted to
    cad19:/home/VLSI_ANALOG/Backup/UMC180/Designkits/Cadence_6.1/lowpower/liberate/decks.cad19.T20210818150829815566S0013820

    *Info* : Initializing SKI environment...
    Initializing Spice
    *Info* Adding 3 global models to Spice.
    Building library database
    ERROR (LIB-203): (char_library): Cell 'ADDFHX1' is scheduled for
    characterization but has no netlist, has an empty subckt or has no
    port on the subckt. This cell will be skipped. Check the netlist and
    rerun.
    ---------- Entering compute template index ------------ Aug 18 15:08:42
    Aug 18 15:08:42 Determining template indices...

    Minimum transition index for the library: 6e-12 sec
    Maximum transition index for the library: 2e-07 sec
    Minimum output capacitance index for the library: 1e-16 F
    Aug 18 15:08:42 Autoindex finished.
    ---------- Exiting compute template index ------------ Aug 18 15:08:42
    WARNING (LIB-961): (char_library): Leakage deck initialization was
    requested using '.ic', but the 'leakage_sim_duration' was set to '0'.
    This may lead to unexpected leakage characterization results. Change
    'leakage_sim_duration' to a positive non-zero value in seconds or
    change the setting of 'set_sim_init_condition' and rerun.
      MEM=861 MB
      MEM=861 MB
      MEM=861 MB

    *Info* (char_library) : SKI process child signal handler disabled.


      MEM=890 MB
    Performance statistics (4 thread(s)):
    Spectre CPU time:     0.00 hours (0.00 seconds)
    Total PreProcessing time:     0.00 hours (0.00 seconds)
    Total cpu time:     0.00 hours (0.00 seconds)
    Wall clock time:     0.00 hours (4.00 seconds)

    Characterization finished at Wed Aug 18 15:08:45 2021

    Characterization statistics:

    Number of cells to characterize =    1
    Number of define_cell commands  =    1
    Number of passing cells         =    0
    Number of failing cells         =    0
    List of failing cells {}
    Number of skipped cells         =    1
    List of skipped cells {ADDFHX1}


    Finished Liberate Execution.
    Updating library database
    /home/VLSI_ANALOG/Backup/UMC180/Designkits/Cadence_6.1/lowpower/liberate/LDB/demoaug.ldb.gz
    Memory usage: 889 Mbytes

    LIBERATE parameter "mx_format_expand_buses" set to "0"
    LIBERATE parameter "ecsm_multi_stage_cap_mode" set to "0"
    LIBERATE parameter "ccsp_mode" set to "0"
    WARNING (LIB-989): (write_library): This command will be skipped
    because there is no cell data to write. Characterize or read the cell
    data and rerun.
    Writing datasheet in text format to
    /home/VLSI_ANALOG/Backup/UMC180/Designkits/Cadence_6.1/lowpower/liberate/DATASHEET/demoaug.txt.txt
    *Error* (write_datasheet) : No cell groups found in the library
    /home/VLSI_ANALOG/Backup/UMC180/Designkits/Cadence_6.1/lowpower/liberate/DATASHEET/demoaug.txt
    no value given for parameter "verilog_filename" (use -help for full usage) :
        verilog_filename string () Output Verilog filename
        while executing
    "OptDoOne descriptions state arguments"
        (procedure "OptDoAll" line 30)
        invoked from within
    "OptDoAll desc arglist"
        (procedure "::tcl::OptKeyParse" line 10)
        invoked from within
    "::tcl::OptKeyParse write_verilog $args"
        (procedure "write_verilog" line 1)
        invoked from within
    "write_verilog -specparams -table_style min-avg-max -cells ${cells}"
        (file "/home/VLSI_ANALOG/Backup/UMC180/Designkits/Cadence_6.1/lowpower/liberate/char.tcl"
    line 40)
    Peak memory usage:          894 MB
    Peak virtual memory usage:  600 MB
    Peak physical memory usage: 293 MB
    Wall time      :    0.00 hours (16.00 seconds)
    LIBERATE exited on cad19 at Wed Aug 18 15:08:45 2021

    Could you please point out where I went wrong?
    Thanks

  • in reply to iamKarthikBK
    iamKarthikBK said:
    WARNING (LIB-162): (define_cell):

    remove PG pins from define_cell command.

    iamKarthikBK said:
    WARNING (LIB-103): When using Spectre-SKI, runtime may significantly
    improve when using an extsim_model_include/define_leafcell flow.

    you may want to act on this warning

    it is always recommended to look into any warnings in the logfile before the error occurs.

    Guangjun

  • in reply to Guangjun Cao

    Sorry I didn't understand what are PG pins. 

    This is my template.tcl

    # Liberate Template Example Tcl File - Sept 2008

    set_var slew_lower_rise 0.2
    set_var slew_upper_rise 0.8
    set_var slew_lower_fall 0.2
    set_var slew_upper_fall 0.8

    set_var measure_slew_lower_rise 0.2
    set_var measure_slew_upper_rise 0.8
    set_var measure_slew_lower_fall 0.2
    set_var measure_slew_upper_fall 0.8

    # Set the minimum and maximum output transition time allowed
    set_var min_transition 6e-12
    set_var max_transition 200e-09
    set_var min_output_cap 1e-16

    set cells { ADDFHX1 }

    define_template -type delay \
            -index_1        {0.250 0.500 0.750 1.250 1.500} \
            -index_2        {0.0150 0.0500 0.1500 0.3000 0.6000} \
            delay_template_5x5

    define_template -type power \
            -index_1        {0.250 0.500 0.750 1.250 1.500} \
            -index_2        {0.0150 0.0500 0.1500 0.3000 0.6000} \
            power_template_5x5

    define_template -type constraint \
            -index_1  {0.250  0.750 1.500} \
            -index_2  {0.250  0.750 1.500} \
            constraint_template_3x3

    set inputs  {A B CI VDD GND}
    set outputs {S CO}
    set clocks  {}
    set asyncs   {}

    Here is my char.tcl: 

    # Liberate Example Tcl File

    # Set the run directory.  Here we use PWD, but in a distributed
    # environment, it is recommended to directly specify the full path
    # instead of using "PWD"
    set rundir $env(PWD)

    # Create the directories Liberate will write to.
    exec mkdir -p ${rundir}/LDB
    exec mkdir -p ${rundir}/LIBRARY
    exec mkdir -p ${rundir}/DATASHEET

    ### Define temperature and default voltage ###
    set_operating_condition -voltage 0.18 -temp 25

    ## Load template information for each cell ##
    source ${rundir}/TEMPLATE/template.tcl

    ## Load Spice models and subckts ##
    set spicefiles $rundir/MODELS/include_tt.sp
    foreach cell $cells {
        lappend spicefiles ${rundir}/NETLIST/${cell}.scs
    }
    read_spice $spicefiles

    ## Characterize the library for NLDM (default), CCS and ECSM timing.
    char_library -auto_index -ccs -ecsm -cells ${cells}

    ## Save characterization database for post-processing ##
    write_ldb ${rundir}/LDB/demoaug.ldb

    ## Generate a .lib with ccs, ecsm ###
    write_library -overwrite  ${rundir}/LIBRARY/demoaug.lib
    ##write_library -overwrite -ecsm ${rundir}/LIBRARY/example_ecsm.lib

    ## Generate ascii datatsheet ###
    write_datasheet -format text ${rundir}/DATASHEET/demoaug.txt

    ## Write Verilog translation ##

    What exactly are PG pins here? Am I supposed to edit the template.tcl?
    Thanks

  • in reply to iamKarthikBK
    iamKarthikBK said:
    I didn't understand what are PG pins

    PowerGround pins. They should be included in your define_cell commands. 

    iamKarthikBK said:
    set inputs  {A B CI VDD GND}

    If 'inputs' is used in your define_cell command, this might be place to change, ie. remove VDD and GND.

    I do not recommend using global variables for any options in define_cell or define_arc commands.  and I do not see any gain by doing so. Instead, it could make the debug harder, esp. when users are not very familiar with Liberate tool/flow/commands.

    Guangjun

  • in reply to Guangjun Cao

    This worked. Thank you so much!

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