How to measure the capacitance of the NMOS used as a varactor

Dear gk1944,

> I am using the circuit shown below. I want to
> have a tuning range of 2-4 GHz for LC VCO.
> I want to use the varactor in this configuration.

> My question:

> 1) How can I find the capacitance of the
> transistors used as a varactor? which analysis
> should I use and which plot will be useful?

I have tried to answer your basic question a number of times in these forums. The most recent of the posts may be found at URL:

community.cadence.com/.../how-to-measure-input-capacitance

The initial contents of that post are included below for your convenience. Let me know if this does not help answer your need to measure the capacitance and I will try to clarify the answer or, if need be, correct my misunderstanding of your question (I hope I understood correctly!),

Dear Holz,

I just answered this question basically in the post at URL:

community.cadence.com/.../test-bench-for-plotting-negative-capacitance-of-cross-coupled-pair

with an example test bench and expressions. You might take a look at this and see how the test bench can include your subcircuit. You only need to set one of your inputs to ground and the other to the included voltage source to, for example, examine the input capacitance when one input is grounded and the other is set to a value of your choosing. In this fashion, you can sweep the variable voltage and determine input capacitance as a function of input voltage - which I am thinking you want to achieve.

I hope this is helpful to you...

Shawn

> 2) To have a tuning range of 2 GHz how many
> stages of such Varactors should I have? is
> there a method or a way to choose this?

I apologize for my comment, but there is not enough information to me to answer this question.

The varactor(s) requirements to achieve a specific tuning range are not usually sufficient in most all VCO applications. Usually, a VCO is an inherent part of a phase-locked loop and hence both the frequency range provided by the varactor(s) and the desired Kvco to achieve the required performance in its phase-locked loop application (loop bandwidth, peaking, phase margin, and supply/crosstalk immunity). Of course, the varactor(s) design will be highly dependent as well on the characteristics of your integrated inductor and the impedance characteristic of your sustaining amplifier.

If I were you, I would start the varactor design process by initially defining all the VCO requirements. Using this information and simulating the impedance characteristics of your inductor and sustaining amplifier will then provide the insight you need to design your varactor network to achieve the design specification. Does this make sense gl1944?

Shawn

Hi Shawn,

Sorry for the last reply. Thanks for your answer.

I am sorry, But the answers were not useful.

I am specifically looking how to simulate a varactor circuit shown above.

I want to know the capacitance at the two ends (gate-bulk short). could you please help me out ?

Dear gk1994.

gk1994 said:

I am sorry, But the answers were not useful.

I am specifically looking how to simulate a varactor circuit shown above.

I am sorry you did not think the "answers" I suggested were not useful. The test bench I provided seems to do exactly what you want, so I am not sure why you did not think it was useful. Perhaps, its use was not clear to you?

I have put a schematic version of your varactor in the test bench I provided in Figure 1. Simply tie the gates to your fixed voltage of 500 mV (voltage source) and sweep voltage source over the range you want. Compute the impedance and determine the capacitance from the imaginary part of the impedance as the expression I provided provides and plot the C-V characteristic. The two resistors are AC resistors and a query of one of them is shown in Figure 2.

I hope this helps clarify the use of the text bench for your specific varactor. I have used this test bench countless number of times as have others.

Shawn

Figure 1

Figure 2