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VerilogA module instance parameter override weird behavior

AAbdelRahman

Hi,

I am using Cadence ICADVM20.1-64b.200.21 with SPECTRE20.1.231.isr6 64bit

I am trying to build a VerilogA model for a (lookup_table) with instance name "I_ACCUM_CLK_GEN_LUT" that is addressed by a modulo (mod_counter) with instance name "I_ACCUM_CLK_ADDRESS_GEN". The read value from this lookup table is then used as clock to another instance of the (mod_counter) called "I_LATCH_CLK_GEN".

All three instances are instantiated in a parent module (mth_residue_estimator) attached

Fullscreen mth_residue_estimator_veriloga.txt Download 
// VerilogA for behavioral_blocks, mth_residue_estimator, veriloga

`include "constants.vams"
`include "disciplines.vams"

module mth_residue_estimator(in, sk_corr, sk_mult, clk_fs, clk_fs_o_Rp1, kth_estim_all_done, out, coeff_done);

input in, sk_corr, sk_mult, clk_fs, clk_fs_o_Rp1, kth_estim_all_done;
output out, coeff_done;
electrical in, sk_corr, sk_mult, clk_fs, clk_fs_o_Rp1, kth_estim_all_done, out, coeff_done;

parameter real out_t_delay = 0 from [0:inf);
parameter real out_t_transition = 10f from [0:inf);
parameter real int_clk_skew = out_t_transition from [0:inf);

parameter integer inherent_clock = 1 from [0:1];
parameter real first_sample_t_delay = 0 from [0:inf);

parameter real clk_f = 3e9;
parameter real vdd = 0.8 from [0:5];
parameter real vclk_threshold = 0.4 from [0:vdd];

parameter integer R = 5 from [0:inf);

electrical latch_clk;
electrical accum_clk, address;

	lookup_table # (.out_t_delay(out_t_delay), .out_t_transition(out_t_transition), .inherent_clock(inherent_clock), .first_sample_t_delay(first_sample_t_delay+int_clk_skew), .clk_f(clk_f), 	.vdd(vdd), .vclk_threshold(vclk_threshold), .size(R+1)) I_ACCUM_CLK_GEN_LUT (.address(address), .rst(latch_clk), .sk_n(sk_corr), .accum_clk(accum_clk));
	mod_counter # (.out_t_delay(out_t_delay), .out_t_transition(out_t_transition), .inherent_clock(inherent_clock), .first_sample_t_delay(first_sample_t_delay), .clk_f(clk_f), 	.vdd(vdd), .vclk_threshold(vclk_threshold), .clk_dir(-1), .modulo(R+1)) I_ACCUM_CLK_ADDRESS_GEN (.clk(clk_fs), .out(address));
	mod_counter # (.out_t_transition(out_t_transition), .inherent_clock(0), .first_sample_t_delay(0), .clk_f(15e9), .clk_dir(1), .modulo(R+1)) I_LATCH_CLK_GEN (.clk(accum_clk), .carry(coeff_done));

endmodule

The mod_counter child module is capable of being triggered by the positive/negative or both edges of an inherent clock (just timers) or an external clock provided via the "clk" input. This is controlled by the "clk_dir" and "inherent_clk" parameters respectively. A generate construct is used.

A $display is used inside each condition to see its inherited parameter values and how the generated behavior will be. All this is shown in the attached code.

Fullscreen mod_counter_veriloga.txt Download 
// VerilogA for behavioral_blocks, mod_counter, veriloga

`include "constants.vams"
`include "disciplines.vams"

module mod_counter(clk, out, carry);

input clk;
output out, carry;
electrical clk, out, carry;

parameter real out_t_delay = 0 from [0:inf);
parameter real out_t_transition = 10f from [0:inf);

parameter integer inherent_clock = 1 from [0:2];
parameter real first_sample_t_delay = 0 from [0:inf);

parameter real clk_f = 3e9;
parameter real vdd = 0.8 from [0:5];
parameter real vclk_threshold = 0.4 from [0:vdd];
parameter integer clk_dir = 1 from [-1:1];

parameter integer modulo = 6 from [0:inf);

integer out_val = 0, carry_val = 0;

analog	@(initial_step)	$display("Modcounter %M: Instance parameters inhereted are:\n\t\tout_t_delay = %g\n\t\tout_t_transition = %g\n\t\tinherent_clock = %d\n\t\tfirst_sample_t_delay = %g\n\t\t\clk_f = %g\n\t\t\vdd = %g\n\t\t\vclk_threshold = %g\n\t\tclk_dir = %d\n\t\tmodulo = %d\n", out_t_delay, out_t_transition, inherent_clock, first_sample_t_delay, clk_f, vdd, vclk_threshold, clk_dir, modulo);

generate
	if (inherent_clock == 1)	begin
		analog	@(initial_step)	$display("Modcounter %M: Entering Inherent clock mode because inherent_clk = %d", inherent_clock);
		case (1)
			(clk_dir == -1) :	begin
									analog	@(initial_step)	$display("Modcounter %M: Inherent clock mode falling edge\n\n");
									analog 	@(timer(first_sample_t_delay+0.5/clk_f,1.0/clk_f))	begin	out_val = (out_val + 1) % modulo; carry_val = (out_val == 0); end
								end
			(clk_dir ==  0) :	begin
									analog	@(initial_step)	$display("Modcounter %M: Inherent clock mode dual edge\n\n");
									analog	@(timer(first_sample_t_delay,0.5/clk_f))			begin	out_val = (out_val + 1) % modulo; carry_val = (out_val == 0); end
								end
			(clk_dir ==  1) :	begin
									analog	@(initial_step)	$display("Modcounter %M: Inherent clock mode rising edge\n\n");
									analog 	@(timer(first_sample_t_delay,1.0/clk_f))			begin	out_val = (out_val + 1) % modulo; carry_val = (out_val == 0); end
								end
		endcase
	end


	else begin
		analog	@(initial_step)	$display("Modcounter %M: Enterinng External clock mode because inherent_clk = %d", inherent_clock);
		if (first_sample_t_delay > 0)	begin
			analog	@(initial_step)	$display("Modcounter %M: Delayed External clock mode");
			electrical int_del_clk;
			analog	V(int_del_clk) <+ absdelay(V(clk),first_sample_t_delay);
			case (1)
				(clk_dir == -1) :	begin
										analog	@(initial_step)	$display("Modcounter %M: Delayed External clock mode falling edge\n\n");
										analog	@(above(vclk_threshold-1e-3-V(int_del_clk))) begin	out_val = (out_val + 1) % modulo;	carry_val = (out_val == 0); end
									end
				(clk_dir ==  0) :	begin
										analog	@(initial_step)	$display("Modcounter %M: Delayed External clock mode dual edge\n\n");
										analog	@(above(vclk_threshold-1e-3-V(int_del_clk)) or above(V(int_del_clk)-vclk_threshold)) begin	out_val = (out_val + 1) % modulo;	carry_val = (out_val == 0); end
									end
				(clk_dir ==  1) :	begin
										analog	@(initial_step)	$display("Modcounter %M: Delayed External clock mode rising edge\n\n");
										analog	@(above(V(int_del_clk)-vclk_threshold)) begin	out_val = (out_val + 1) % modulo;	carry_val = (out_val == 0); end
									end
			endcase
		end
		else	begin
			analog	@(initial_step)	$display("Modcounter %M: Non delayed External clock mode");
			case (1)
				(clk_dir == -1) :	begin
										analog	@(initial_step)	$display("Modcounter %M: Non delayed External clock mode falling edge\n\n");
										analog	@(above(vclk_threshold-1e-3-V(clk))) begin	out_val = (out_val + 1) % modulo;	carry_val = (out_val == 0); end
									end
				(clk_dir ==  0) :	begin
										analog	@(initial_step)	$display("Modcounter %M: Non delayed External clock mode dual edge\n\n");
										analog	@(above(vclk_threshold-1e-3-V(clk)) or above(V(clk)-vclk_threshold)) begin	out_val = (out_val + 1) % modulo;	carry_val = (out_val == 0); end
									end
				(clk_dir ==  1) :	begin
										analog	@(initial_step)	$display("Modcounter %M: Non delayed External clock mode rising edge\n\n");	
										analog	@(above(V(clk)-vclk_threshold)) begin	out_val = (out_val + 1) % modulo;	carry_val = (out_val == 0); end
									end
			endcase
		end
	end


	analog begin
		V(out)		<+ transition(out_val,	out_t_delay, out_t_transition, out_t_transition);
		V(carry)	<+ transition(vdd*carry_val,	out_t_delay, out_t_transition, out_t_transition);
	end
endgenerate

endmodule

Finally, the lookup_table is attached below.

Fullscreen lookup_table_veriloga.txt Download 
// VerilogA for behavioral_blocks, lookup_table, veriloga

`include "constants.vams"
`include "disciplines.vams"

module lookup_table(address, clk, rst, sk_n, accum_clk);

input address, clk, rst, sk_n;
output accum_clk;
electrical address, clk, rst, sk_n, accum_clk;

parameter real out_t_delay = 0 from [0:inf);
parameter real out_t_transition = 10f from [0:inf);

parameter integer inherent_clock = 1 from [0:1];
parameter real first_sample_t_delay = 0 from [0:inf);

parameter real clk_f = 3e9;
parameter real vdd = 0.8 from [0:5];
parameter real vclk_threshold = 0.4 from [0:vdd];

parameter integer size = 6 from [0:inf);

integer saved_value[0:size-1];
integer address_val = 0;
integer set_val = 1;
integer sk_n_val = 0;
integer data_read_val = 0;
integer accum_clk_val = 0;

integer k = 0;

generate
	if (inherent_clock == 1) begin
		analog begin
			@(timer(first_sample_t_delay+0.5/clk_f,1.0/clk_f)) begin
				if (V(rst) < vclk_threshold && set_val)	saved_value[address_val] = 1;			// If read data was low and sk is high (i.e, setval is high) --> set the addressed register high.
				address_val = V(address);														// Update the address register
				data_read_val = saved_value[address_val];										// Read the data from the new address (not clocked in reality)
				sk_n_val = V(sk_n);															// Update the sk info you have (not clocked in reality) (needs to be done for both clock edges as it will be read during both)
				set_val = sk_n_val && (!data_read_val);										// Update the setval register accordingly (needs to be done for both clock edges as it will be read during both)
				accum_clk_val = 0;															// Lower the accum_clk_val as the clock is now supposed to be low (gated by the clock)
			end
			@(timer(first_sample_t_delay,1.0/clk_f))	begin
				sk_n_val = V(sk_n);															// Update the sk info you have (not clocked in reality) (needs to be done for both clock edges as it will be read during both)
				set_val = sk_n_val && (!data_read_val);										// Update the setval accordingly (not clocked with this edge in reality) (needs to be done for both clock edges as it will be 
				accum_clk_val = set_val;														// Calculate Whether to clock the accumulator or not
			end
		end
	end
	else	begin
		if (first_sample_t_delay > 0) begin
			electrical int_del_clk;
			analog begin
				V(int_del_clk) <+ absdelay(V(clk),first_sample_t_delay);
				@(above(vclk_threshold-1e-3-V(int_del_clk))) begin
					if (V(rst) < vclk_threshold && set_val)	saved_value[address_val] = 1;		// If read data was low and sk is high (i.e, setval is high) --> set the addressed register high.
					address_val = V(address);													// Update the address register
					data_read_val = saved_value[address_val];									// Read the data from the new address (not clocked in reality)
					sk_n_val = V(sk_n);														// Update the sk info you have (not clocked in reality) (needs to be done for both clock edges as it will be read during both)
					set_val = sk_n_val && (!data_read_val);									// Update the setval register accordingly (needs to be done for both clock edges as it will be read during both)
					accum_clk_val = 0;														// Lower the accum_clk_val as the clock is now supposed to be low (gated by the clock)
				end
				@(above(V(int_del_clk)-vclk_threshold)) begin
					sk_n_val = V(sk_n);														// Update the sk info you have (not clocked in reality) (needs to be done for both clock edges as it will be read during both)
					set_val = sk_n_val && (!data_read_val);									// Update the setval accordingly (not clocked with this edge in reality) (needs to be done for both clock edges as it will be 
					accum_clk_val = set_val;													// Calculate Whether to clock the accumulator or not
				end
			end
		end
		
		else begin
			analog begin
				@(above(vclk_threshold-1e-3-V(clk))) begin
					if (V(rst) < vclk_threshold && set_val)	saved_value[address_val] = 1;		// If read data was low and sk is high (i.e, setval is high) --> set the addressed register high.
					address_val = V(address);													// Update the address register
					data_read_val = saved_value[address_val];									// Read the data from the new address (not clocked in reality)
					sk_n_val = V(sk_n);														// Update the sk info you have (not clocked in reality) (needs to be done for both clock edges as it will be read during both)
					set_val = sk_n_val && (!data_read_val);									// Update the setval register accordingly (needs to be done for both clock edges as it will be read during both)
					accum_clk_val = 0;														// Lower the accum_clk_val as the clock is now supposed to be low (gated by the clock)
				end
				@(above(V(clk)-vclk_threshold)) begin
					sk_n_val = V(sk_n);														// Update the sk info you have (not clocked in reality) (needs to be done for both clock edges as it will be read during both)
					set_val = sk_n_val && (!data_read_val);									// Update the setval accordingly (not clocked with this edge in reality) (needs to be done for both clock edges as it will be 
					accum_clk_val = set_val;													// Calculate Whether to clock the accumulator or not
				end
			end
		end
	end

endgenerate

analog begin

	@(above(V(rst)-vclk_threshold)) for (k = 0; k < size; k = k+1) saved_value[k] = 0;
	V(accum_clk) <+ transition(vdd*accum_clk_val, out_t_delay, out_t_transition, out_t_transition);
end


endmodule

Case 1 (netlist attached below):

When any number of (mod_counter) modules are tested alone at the top level to see if the module acts as expected, it indeed works correctly for all combinations of "inherent_clk" and "clk_dir". This can be guaranteed by the outputs of the $display in the output log shown below

Case2 (netlist attached below):

However, when 2 (mod_counters) are instantiated inside the (mth_residue_estimator) as shown above and an instance of (mth_residue_estimator) is tested, I got a weird behavior.

Both counters inside work as if they are in the inherent_clock rising edge mode, i.e., as if "inherent_clock" = 1 and "clk_dir" = 1 which are the default values of those parameters inside (mod_counter) module, although the values for these parameters are different for both instances during instantiation and the $display statements say that the inherited values are correct.

Basically what is happening is that both instances of (mod_counter) take the parameter values correctly from the parent instantiator module (mth_residue_estimator) and then ignore them totally and use the default values to use in the conditional generate blocks for some unknown reason.

Case 3 (netlist attached below):

This also happens to any module of (mod_counter) instantiated outside (mth_residue_estimator) but in its presence in the netlist. Here I used the same instances instantiated in Case 1 above with their parameters unchanged.

Although they worked correctly before when (mth_residue_estimator) wasn't there in the netlist. I5, I4 and I1 are now behaving incorrectly in the presence of I61.



Netlists

Case 1:

Fullscreen netlist_case1.txt Download 
// Point Netlist Generated on: Dec 23 10:04:40 2021
// Generated for: spectre
// Design Netlist Generated on: Dec 23 10:04:40 2021
// Design library name: altair_DAC
// Design cell name: tb_residue_estimator
// Design view name: schematic
simulator lang=spectre
global 0
include "$SPECTRE_MODEL_PATH/design_wrapper.lib.scs" section=tt_pre
parameters R=5 clk_dir=-1 clk_f=3G clk_tf=(0.02 / clk_f) clk_tr=(0.02 / \
    clk_f) sim_tran_tstp=(1000 / clk_f)

// Library name: altair_DAC
// Cell name: tb_residue_estimator
// View name: schematic
V3 (sk_n 0) vsource dc=1 type=dc
V5 (net1 0) vsource dc=1 type=dc
V37 (clk_fs 0) vsource type=pulse val0=0 val1=800.0m period=1/clk_f \
        delay=-clk_tr/2 rise=clk_tr fall=clk_tf \
        width=0.5*((1/clk_f)-(clk_tr)-(clk_tf))
I5 (net5 out_inh carry_inh) mod_counter out_t_delay=0 \
        out_t_transition=clk_tr inherent_clock=1 \
        first_sample_t_delay=clk_tr clk_f=clk_f vdd=0.8 vclk_threshold=0.4 \
        clk_dir=clk_dir modulo=6
I4 (sk_n out_ext_nondel carry_ext_nondel) mod_counter out_t_delay=0 \
        out_t_transition=clk_tr inherent_clock=0 first_sample_t_delay=0 \
        clk_f=clk_f vdd=0.8 vclk_threshold=0.4 clk_dir=clk_dir modulo=6
I1 (sk_n out_ext carry_ext) mod_counter out_t_delay=0 \
        out_t_transition=clk_tr inherent_clock=0 \
        first_sample_t_delay=clk_tr clk_f=clk_f vdd=0.8 vclk_threshold=0.4 \
        clk_dir=clk_dir modulo=6
simulatorOptions options psfversion="1.4.0" reltol=1e-3 vabstol=1e-6 \
    iabstol=1e-12 temp=27 tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 \
    vthmod=vthcc ivthn=300e-9 ivthp=70e-9 ivthw=0 ivthl=0 maxnotes=5 \
    maxwarns=5 digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf vdsatmod=gds 
tran tran stop=sim_tran_tstp errpreset=conservative write="spectre.ic" \
    writefinal="spectre.fc" annotate=status maxiters=5 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=all saveahdlvars=all
ahdl_include "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/mod_counter/veriloga/veriloga.va"

Case 2:

Fullscreen netlist_case2.txt Download 
// Point Netlist Generated on: Dec 23 10:11:13 2021
// Generated for: spectre
// Design Netlist Generated on: Dec 23 10:11:12 2021
// Design library name: altair_DAC
// Design cell name: tb_residue_estimator
// Design view name: schematic
simulator lang=spectre
global 0
include "$SPECTRE_MODEL_PATH/design_wrapper.lib.scs" section=tt_pre
parameters R=5 clk_dir=-1 clk_f=3G clk_tf=(0.02 / clk_f) clk_tr=(0.02 / \
    clk_f) sim_tran_tstp=(1000 / clk_f)

// Library name: altair_DAC
// Cell name: tb_residue_estimator
// View name: schematic
V3 (sk_n 0) vsource dc=1 type=dc
V5 (net1 0) vsource dc=1 type=dc
I61 (net1 sk_n sk_n clk_fs clk_fs_o_Rp1 0 out_mth done_mth) \
        mth_residue_estimator out_t_delay=0 out_t_transition=clk_tr \
        int_clk_skew=clk_tr inherent_clock=1 first_sample_t_delay=0 \
        clk_f=clk_f vdd=0.8 vclk_threshold=0.4 R=R
V37 (clk_fs 0) vsource type=pulse val0=0 val1=800.0m period=1/clk_f \
        delay=-clk_tr/2 rise=clk_tr fall=clk_tf \
        width=0.5*((1/clk_f)-(clk_tr)-(clk_tf))
simulatorOptions options psfversion="1.4.0" reltol=1e-3 vabstol=1e-6 \
    iabstol=1e-12 temp=27 tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 \
    vthmod=vthcc ivthn=300e-9 ivthp=70e-9 ivthw=0 ivthl=0 maxnotes=5 \
    maxwarns=5 digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf vdsatmod=gds 
tran tran stop=sim_tran_tstp errpreset=conservative write="spectre.ic" \
    writefinal="spectre.fc" annotate=status maxiters=5 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=all saveahdlvars=all
ahdl_include "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/mth_residue_estimator/veriloga/veriloga.va"
ahdl_include "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/mod_counter/veriloga/veriloga.va"
ahdl_include "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/lookup_table/veriloga/veriloga.va"

Case 3:

Fullscreen netlist_case3.txt Download 
// Point Netlist Generated on: Dec 23 10:13:33 2021
// Generated for: spectre
// Design Netlist Generated on: Dec 23 10:13:33 2021
// Design library name: altair_DAC
// Design cell name: tb_residue_estimator
// Design view name: schematic
simulator lang=spectre
global 0
include "$SPECTRE_MODEL_PATH/design_wrapper.lib.scs" section=tt_pre
parameters R=5 clk_dir=-1 clk_f=3G clk_tf=(0.02 / clk_f) clk_tr=(0.02 / \
    clk_f) sim_tran_tstp=(1000 / clk_f)

// Library name: altair_DAC
// Cell name: tb_residue_estimator
// View name: schematic
V3 (sk_n 0) vsource dc=1 type=dc
V5 (net1 0) vsource dc=1 type=dc
I61 (net1 sk_n sk_n clk_fs clk_fs_o_Rp1 0 out_mth done_mth) \
        mth_residue_estimator out_t_delay=0 out_t_transition=clk_tr \
        int_clk_skew=clk_tr inherent_clock=1 first_sample_t_delay=0 \
        clk_f=clk_f vdd=0.8 vclk_threshold=0.4 R=R
V37 (clk_fs 0) vsource type=pulse val0=0 val1=800.0m period=1/clk_f \
        delay=-clk_tr/2 rise=clk_tr fall=clk_tf \
        width=0.5*((1/clk_f)-(clk_tr)-(clk_tf))
I5 (net5 out_inh carry_inh) mod_counter out_t_delay=0 \
        out_t_transition=clk_tr inherent_clock=1 \
        first_sample_t_delay=clk_tr clk_f=clk_f vdd=0.8 vclk_threshold=0.4 \
        clk_dir=clk_dir modulo=6
I4 (sk_n out_ext_nondel carry_ext_nondel) mod_counter out_t_delay=0 \
        out_t_transition=clk_tr inherent_clock=0 first_sample_t_delay=0 \
        clk_f=clk_f vdd=0.8 vclk_threshold=0.4 clk_dir=clk_dir modulo=6
I1 (sk_n out_ext carry_ext) mod_counter out_t_delay=0 \
        out_t_transition=clk_tr inherent_clock=0 \
        first_sample_t_delay=clk_tr clk_f=clk_f vdd=0.8 vclk_threshold=0.4 \
        clk_dir=clk_dir modulo=6
simulatorOptions options psfversion="1.4.0" reltol=1e-3 vabstol=1e-6 \
    iabstol=1e-12 temp=27 tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 \
    vthmod=vthcc ivthn=300e-9 ivthp=70e-9 ivthw=0 ivthl=0 maxnotes=5 \
    maxwarns=5 digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf vdsatmod=gds 
tran tran stop=sim_tran_tstp errpreset=conservative write="spectre.ic" \
    writefinal="spectre.fc" annotate=status maxiters=5 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=all saveahdlvars=all
ahdl_include "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/mth_residue_estimator/veriloga/veriloga.va"
ahdl_include "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/mod_counter/veriloga/veriloga.va"
ahdl_include "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/lookup_table/veriloga/veriloga.va"

I hope someone could help.

Best,

Ahmed

  • Ahmed,

    I was going to spend a little time looking through this (it's hard to follow because of the stream of text with modules and narrative along the way), but given you've not given the code for lookup_table or how the simulation is setup, it's really not worth me trying to test and guess what's going on. It's going to take more than a quick investigation, and there's a high chance I wouldn't be repeating your problem because of insufficient information.

    I suggest you contact customer support.

    Regards,

    Andrew

  • in reply to Andrew Beckett

    Hi Andrew,

    Thanks for replying.

    This is my first post in Cadence forums. So, I am still struggling a little bit with how to put a code inside my post without it being treated the same way as normal text. I tried to use the <code></code> but apparently it didn't work

    I thought that including the files as text wouldn't show their contents in the post which is a thing I wanted to do. After your reply I thought to myself I will do it anyways. I didn't know that it really puts them inline in a neat format.

    So, here it is.

    I edited the post again after this text file upload thing and I also added all my netlists.

    I did that for the sake of completeness and still, I would really appreciate it if you gave it another look.

    Thanks for what you are doing. I really appreciate it.

    Best regards,

    Ahmed

  • in reply to AAbdelRahman

    Ahmed,

    This is a bug related to handling of generate statements when there are hierarchical instances within VerilogA. I've reproduced your issue.

    I'll file a change request for this later today as I spent the time reproducing it. I know that contacting customer support is tricky for you (from your other post).

    Regards,

    Andrew

  • in reply to Andrew Beckett

    Ahmed,

    The change request is CCR 2590873.

    Andrew

  • in reply to Andrew Beckett

    Hi Andrew,

    I really appreciate your help.

    Thanks again.

    Best regards,

    Ahmed

  • in reply to AAbdelRahman

    Hi Ahmed,

    R&D found the bug and have fixed it. The plan is for it to be in SPECTRE20.1 ISR15, which should be available around the end of February (I don't have a date yet, so this is just extrapolation). The issue was caused by using named (explicit) connections in the hierarchical instances within mth_residue_estimator. If instead you use positional (implicit) connections then the problem goes away - i.e. changing to:

    Fullscreen mth_residue_estimator_veriloga_order.txt Download 
    // VerilogA for behavioral_blocks, mth_residue_estimator, veriloga

`include "constants.vams"
`include "disciplines.vams"

module mth_residue_estimator(in, sk_corr, sk_mult, clk_fs, clk_fs_o_Rp1, kth_estim_all_done, out, coeff_done);

input in, sk_corr, sk_mult, clk_fs, clk_fs_o_Rp1, kth_estim_all_done;
output out, coeff_done;
electrical in, sk_corr, sk_mult, clk_fs, clk_fs_o_Rp1, kth_estim_all_done, out, coeff_done;

parameter real out_t_delay = 0 from [0:inf);
parameter real out_t_transition = 10f from [0:inf);
parameter real int_clk_skew = out_t_transition from [0:inf);

parameter integer inherent_clock = 1 from [0:1];
parameter real first_sample_t_delay = 0 from [0:inf);

parameter real clk_f = 3e9;
parameter real vdd = 0.8 from [0:5];
parameter real vclk_threshold = 0.4 from [0:vdd];

parameter integer R = 5 from [0:inf);

electrical latch_clk;
electrical accum_clk, address;

	lookup_table # (.out_t_delay(out_t_delay), .out_t_transition(out_t_transition), .inherent_clock(inherent_clock), .first_sample_t_delay(first_sample_t_delay+int_clk_skew), .clk_f(clk_f), 	.vdd(vdd), .vclk_threshold(vclk_threshold), .size(R+1)) I_ACCUM_CLK_GEN_LUT (.address(address), .rst(latch_clk), .sk_n(sk_corr), .accum_clk(accum_clk));
	mod_counter # (.out_t_delay(out_t_delay), .out_t_transition(out_t_transition), .inherent_clock(inherent_clock), .first_sample_t_delay(first_sample_t_delay), .clk_f(clk_f), 	.vdd(vdd), .vclk_threshold(vclk_threshold), .clk_dir(-1), .modulo(R+1)) I_ACCUM_CLK_ADDRESS_GEN (clk_fs, address, dummy_carry);
	mod_counter # (.out_t_transition(out_t_transition), .inherent_clock(0), .first_sample_t_delay(0), .clk_f(15e9), .clk_dir(1), .modulo(R+1)) I_LATCH_CLK_GEN (accum_clk,dummy_out,coeff_done);

endmodule

    So hopefully that can be used as a workaround in the meantime until the fix is available.

    Regards,

    Andrew

  • in reply to Andrew Beckett

    Hi Andrew,

    My thanks to you and the R&D team.

    Best regards,

    Ahmed

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