Verilog-A Parser shows an error but simulation runs successfully with 0 errors

This is an aspect of the fact that Virtuoso doesn't really directly support variable width buses (either in schematics or in Verilog-A models). In older versions of Spectre, the analyser gave errors such as you were seeing. These went away in Spectre18.1 ISR12, but then you hit a different problem that both the shadow database used to store the terminal information, plus any generated symbols end up with the wrong bus width (not even the default value).

A workaround is to use the approach covered in my article How to create a VerilogA model of a DAC with a variable width bus input

Regards,

Andrew

This is an aspect of the fact that Virtuoso doesn't really directly support variable width buses (either in schematics or in Verilog-A models). In older versions of Spectre, the analyser gave errors such as you were seeing. These went away in Spectre18.1 ISR12, but then you hit a different problem that both the shadow database used to store the terminal information, plus any generated symbols end up with the wrong bus width (not even the default value).

A workaround is to use the approach covered in my article How to create a VerilogA model of a DAC with a variable width bus input

Regards,

Andrew

Thank you for your fast reply Andrew. I will have a look at the provided link.

Just as a comment or for documentation purposes (I was preparing this before you replied):
In the example above I wanted to use an Analog Contribution inside the for loop to pass values only to some indexes of the port, in this case to indexes 0 to 3.

Well, it seems that the Verilog-A Parser doesn't like it and shows an error.
I would have expected a Warning, not an error because as mentioned in the initial message the simulation runs without problems.

I did some changes in the code so that I pass values to all the indexes of the port, from 0 to 7, and now the Verilog-A Parser doesn't complain.
But this is not necessarily what I wanted to do.

Thank you very much!

See new code below:

`include "constants.vams"
`include "disciplines.vams"

module dut (out, in);

// Parameters
parameter integer width = 8;

// Port Direction
output [width-1:0] out;
input [width-1:0] in;

// Port Type/Discipline
electrical [width-1:0] out;
electrical [width-1:0] in;

parameter real td = 0;
parameter real tt = 1n;

//~ real value [3:0];
real value [width-1:0];

genvar i;

analog begin

@(initial_step) begin
value[7] = 7.8;
value[6] = 6.8;
value[5] = 5.8;
value[4] = 4.8;
value[3] = 3.5;
value[2] = 2.6;
value[1] = 1.7;
value[0] = 0.8;
end

//~ for (i=0; i<=3; i=i+1) begin
for (i=0; i<width; i=i+1) begin
V(out[i]) <+ transition(value[i], td, tt);
end

end

endmodule