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ignore instance by layout extraction

Senan

Hello,

I use the  iprobe that break the feedback loop of the amplifier in my design to perform the stability analyses,

Now I am doing the layout, but don't know how to make the iprobe ignored by the layout so I can pass the LVS, then later I will be able to use this probe for my post-layout simulation.

I use the Cadence Virtuoso version IC6.18-64b.500.6 with Assura package

Thank you in advance

Best Regards

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  • drdanmc

    Another way to do it is create a stability cell.  The schematic and layout view are a metal resistor placed per the solution that Andrew linked.  Include a second schematic view called something like `schematic_stb` or something.  When running LVS blackbox that cell and you can then use the hierarchy editor to select the `schematic_stb` view for it.  Yet another way to do it is use a custom QRC `avExtractedCellViewCallProc` function that does the replacement of the metal resistor directly during extracted view creation.  If you try the last way just be aware that it will take some amount of SKILL programming.  I tend to prefer the blackbox approach.

  • drdanmc
    in reply to drdanmc

    I seem to have omitted that the `schematic_stb` view has the `iprobe` instance.

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  • drdanmc
    in reply to drdanmc

    I seem to have omitted that the `schematic_stb` view has the `iprobe` instance.

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