Simulating Config with veriloga view set, does not simulate the veriloga version but still runs the schematic.

That's very odd and should not be necessary. I'm rather surprised that you're seeing this because this should be robust and I've not seen this elsewhere (other than some user mistake where the design was really not set to be the config, or there was a mistake in the config).

Can you contact customer support please? That's going to be the fastest way of seeing what is going on and identifying how to fix it.

Regards,

Andrew

Thanks Andrew, Shawn.
To be honest I don't think I've ever had this running without issues,  so I must be doing something odd.
It all worked perfectly with AMS, but not with Spectre/ADL/Veriloga,  I think (though it's now 3 years ago) that I always had to manually insert the path to the VA file for spectre simulations.

As far as I remember, the problem only ever occurred when there's a schematic too.  When there's only a veriloga and symbol, I think it worked OK.  But that's the whole point of incremental design,  being able to switch views to see how the design deviates from the 'ideal'.

As you say Andrew, it should just work, I'm not sure what I do that's messing it all up.

@Shawn, yes I've checked...(FYI, I've been using Cadence tools since 1990, but of course we still make mistakes, so it's worth repeating the obvious).

In the run.log I see this for the run.

Simulating `input.scs' on server at 11:03:42 AM, Thur Mar 31, 2022 (process id: 300).
Current working directory: xxx/cds_sim/MySimBenches/test_lvlsh/spectre/config_va/netlist
Command line:
\
/tools/external/cadence/spectre/17/17.10.389/tools.lnx86/bin/spectre \
-64 input.scs +escchars +log ../psf/spectre.out -format psfxl \
+rtsf -raw ../psf ++aps +lqtimeout 900 -maxw 5 -maxn 5 +lorder \
MMSIM +lqt 0 +lqs 30 +lsuspend +lqmmtoken

But the netlist still shows ...

// Library name: __tmpLib
// Cell name: itrx_can_vss_lvlshft
// View name: __tmpView
// Inherited view list: spectre veriloga cmos_sch cmos.sch schematic ahdl
// pspice dspf
subckt itrx_can_vss_lvlshft IN BYP OUT OUT_n SUB VDD VSD VDP VSP
MN10 (VSD inp VDD inn VSD SUB) nmos_5p0_dw_6T_pcell_0 \
pf1va_width=3.460u pf1va_length=2.045u mx=1 dnw_width=9.460u \
dnw_length=8.045u fingerW=845.000n nf=2 l=600n sArea=0.5746p \

So still net listing the schematic.

@Andrew,
Not sure how easy it is for me to use Cadence Support, since I'm on a temporary placement at the company.
So I've not got anything set up for Cadence support just now.

Sorry. The config view should have been..

Dear JohnTweed,

Why is your view list starting with the "spectre" view? I usually place the "spectre" view as the last view to examine as it is the stopping point for views.

In other words, move the "spectre" to after, for example "schemaic". Have you tried that?

Shawn

That is how the Spectre Template populates the View List.

I think that the ordering of Spectre & Schematic will only disrupt special cases where you have a model and a schematic view together. But then, that is what I have here, except my 'model' is a veriloga file.  The main difference however, is that models are imported in a model library file.

But, it's worth a try.
I'll get back to you tomorrow.

That is how the Spectre Template populates the View List.

I think that the ordering of Spectre & Schematic will only disrupt special cases where you have a model and a schematic view together. But then, that is what I have here, except my 'model' is a veriloga file.  The main difference however, is that models are imported in a model library file.

But, it's worth a try.
I'll get back to you tomorrow.

Thanks for including the netist - I spotted that it looked rather strange and was showing __tmpLib and __tmpView as the library and view names in the comments which allowed me to search and I found that there is an experimental feature (which has not been released and has a number of problems) which was added for one customer in particular (given their location in the world I suspect it's not that company you're at, so not sure why the setting has been enabled there). Anyway, I believe you have the variable:

hnlUseSchematicForInherittedConnection

set to t (yes, there's a spelling mistake in the variable name). This variable should not be used - it was specifically to deal with a requirement related to inherited connections with the Verilog netlister and clearly breaks the spectre netlister (I'll report this to R&D, but they will undoubtedly ask me why it is being set in the first place).

Try setting:

hnlUseSchematicForInherittedConnection=nil

and then recreating the netlist - see if that fixes it. You should ask within your company why this is being set and get them to contact us about it.

At least I hope this is the reason. I was able to reproduce the problem by setting the variable...

Andrew

Oh and having spectre at the beginning of the viewList is perfectly fine - it would only make a difference if you have a spectre view and one of the other views, and even then it would depend upon your preference as to which should be picked by default. It can't affect this.

Andrew

Thanks Andrew for your (always) helpful responses,
Will try that later today and report back.
If it works, I'll get someone in my company to check the setting.

Hi Andrew,
Sorry, but no luck with that.  
First I tried checking that hnlUseSchematicForInherittedConnection variable and Cadence responded with 'variable not set'
I set it anyway in my .cdsinit (along with a print, to be sure).

But no luck,  still the same result, that it's the schematic version.

Here's the relevant bit of the CDS.log for the simulation.

\a sevNetlistAndRun('sevSession1)
\o Delete psf data in /local/users/user/cds_sim/MySimBenches/test_lvlsh/spectre/config_va/psf.
\o generate netlist...
\o Loading seCore.cxt
\o Begin Incremental Netlisting Apr 1 07:53:30 2022
\o {07:53:30} (IPC command) "svn --config-dir=/bach/users/user/.methodics/versic/subversion info --non-interactive /local/users/user/workspaces/project/trunk/cds_run/__tmpLib" [log:/tmp/user-versic/vscIPC_15399_bi]
\o {07:53:32} (system call) "find /local/users/user/workspaces/project/trunk/cds_run/__tmpLib -name .svn | xargs rm -rf"
\w *WARNING* (DB-260008): dbOpenBag: Fail to open prop. bag for '__tmpLib' in 'r' mode, file not found
\w *WARNING* (DB-260005): dbCloseBag: Invalid bagID - nil
\o INFO (TECH-1000002): Attaching default techfile (cdsDefTechLib) to library __tmpLib.
\o WARNING (OSSHNL-169): The property bag for the library '__tmpLib', has been modified or added since the
\o last netlisting session. Therefore, re-netlisting all the cell views used from
\o this library as well as all the cell views where instances of cell views from
\o this library are used.
\o
\o End netlisting Apr 1 07:53:34 2022
\w *WARNING* ddStartGenObjRel: argument must be Lib, Cell or View; found ddViewFileType.
\w *WARNING* ddStartGenObjRel: argument must be Lib, Cell or View; found ddViewFileType.
\w *WARNING* ddStartGenObjRel: argument must be Lib, Cell or View; found ddViewFileType.
\o Loading monte.cxt
\o
\o Netlisting Statistics:
\o Number of components: 19
\o
\o Elapsed time: 7.0s (2.71/s)
\o Errors: 0 Warnings: 0
\o ...successful.
\o compose simulator input file...
\o ...successful.
\o start simulator if needed...
\o ...successful.
\o simulate...

Just to be sure it's not me :-)...  I closed the ADL,  reopen ADL again with the design=config_va, but this time as an AMS simulation. Reload the spectre state for the tran settings, models etc.
The Netlist&run AMS.
Works exactly as it says on the box...

But for now I suppose, every time I want to try something out with veriloga in place of the schematic I can just run AMS.  It's a work around, but I'm not supposed to be spending much time on this.

I'll ask one of my full-time colleagues to also try this to see if they also experience this issue.  If they do, then they can initiate the conversation with Cadence Support.

Andrew, it seems that this is too opaque to be handled within the forum.  So it'll have to wait till someone has time to address it.

Thanks for your suggestion.
 

I'm wondering whether it's maybe being set in a .simrc - but that doesn't quite explain how it ends up unset (if set in a .simrc then setting in your .cdsinit wouldn't be enough because it would get clobbered by the .simrc setting). The symptoms absolutely match the behaviour of that variable, including the complaints about __tmpLib.

I think it would be best to follow this up with customer support via one of your full-time colleagues, since debugging this via the forums will be hard - especially as this is a rather esoteric non-production setting and I can't see any other way of it getting stuck in that part of the code. Maybe the behaviour was different in the specific IC6.1.8 sub-version you're using (I was using the very latest, ISR24) - getVersion(t) in the CIW or Help->About will report that (I can do a little more digging if I know the sub-version)

Andrew

Hi Andrew,

Thanks for your time,  version is 500.11
I'll look at .simrc but not hopeful.  I was a completely fresh setup, so had no time to tweak things like I used to do, which did cause problems for Cadence support from time to time. The addage 'a little knowledge...' comes to mind.

But this is the vanilla Cadence for this company AFIK, they don't have a lot of company experts 'improving' the basic Cadence setup, like in my previous life.

I'd just leave it for now,  I was hoping for a 'duhhh' moment, 'You didn't do this or that'.
I can just run AMS if I want to try a mixed config.
Regards.