Ignoring instances in the layout during LVS (and/or DRC)

Hi delgsy

What I usually do is adding the equivalent instant in the schematic. For example, if we have an array of capacitors, we typically use some dummy capacitors around that array to prevent mismatch-related issues. We can use this dummy cap in the schematic as well and connect it to nowhere or short circuit it. If that part of the layout is not a technology component, you can easily create an instance of that layout and create a symbol for that so you can use it in the schematic. In this way, LVS passes and there is no confusion for someone who reads your schematic.

You didn't mention which LVS tool you're using. You can't do this by adding the lvsIgnore property on the layout - the stream file will be created anyway with the instance. The lvsIgnore property is for the schematic - it's not so common that you'd have layout but no schematic.

You can achieve this with PVS for example. Create a file called "exclude.rul" containing:

exclude_cell cellNameYouWantToIgnore

(the line can list multiple cell names) and then add this as an additional rule file when running LVS (or DRC).

You can probably achieve the same idea in other LVS tools, but I wasn't going to try to find an exhaustive answer for all possible LVS tools!

Andrew

Hello Andrew,
Your solution works for PVS! Thank you!

Do you happen to know the equivalent command for Calibre?

I tried "EXCLUDE CELL" command but it does not work.

I am aware I should have asked it in Calibre forum and I did.
But either I post in a wrong thread or the forum is not as active as this forum.
This is from Calibre manual.

delgsy said:

Do you happen to know the equivalent command for Calibre?

Er, no, because Calibre is a Siemens EDA product and I have no access to it... which is really why you should be asking on a Siemens EDA forum! Others may be able to help you, maybe.

Andrew