Cellview generation from VHDL code in cadence 618

A few questions:

1. Which IC sub-version are you using? (Help->About in any window will tell you)
2. Do you have "XCELIUM" (or "INCISIVE" - although that's unsupported now) in your UNIX path? i.e. what do you get if you type "xrun -version" or "irun -version" in the terminal window?
3. It suggested you look at the Parser Log File - did you look at this, and what did it say?
4. Can you share the VHDL code you were trying to add?

Otherwise, you've given an error message indicating that something is wrong with the code, without sharing what the code is and what the errors were. Pretty hard for anyone to diagnose that other than suggesting you do what the message said and look at the parser log file!

Andrew

Hi Andrew B,

1. IC Version : IC 6.1.8-64b.500.26

2. I am unable to run xrun, i tried to run in CIW command editor...seems this is not correct way, pls help me out for this.

3. parser log file was blank file ...nothing here

4. 

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 07/26/2022 05:56:16 PM
-- Design Name: 
-- Module Name: cnt_CTIA - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith;
use ieee.std_logic_unsigned.all;

entity cnt_CTIA is
 Port (
 clk,ramp_enbl,comp_out,reset : in std_logic;
 count : out std_logic_vector (9 downto 0)

  );
end cnt_CTIA;

architecture Behavioral of cnt_CTIA is
signal cntr_dir : std_logic;
signal q1: std_logic_vector (9 downto 0);
begin
process (ramp_enbl,reset)
    begin
    if (reset = '1') then      
      cntr_dir <= '1';       
    elsif (ramp_enbl'event and ramp_enbl = '1') then
    cntr_dir <= not cntr_dir;
    end if;
end process;

--process (cntr_dir)
--begin
--if (cntr_dir'event and cntr_dir = '0') then
--   count <= q1;
--  q1 <= (others => '0');
--   end if; 
--end process;

process (clk,reset)
begin
if (reset = '1') then
    q1 <= (others => '0');

elsif (clk'event and clk = '1') then
    if (comp_out = '1') then
        if ((ramp_enbl and comp_out) = '1') then
               if (cntr_dir = '0')then
                q1 <=  q1 +1;
                else 
                q1 <=  q1 -1;
                end if;
            else
            q1 <=  q1;
            end if;
         else
      q1 <=  q1;
     end if;
end if;
end process;
count <= q1;
end Behavioral;

Note : I even tried the verilog editor for simple inverter code

(module veri (
input x,
output y);
assign y = x;
endmodule) ;

following is error/warning log

Error* _gets: argument #1 should be an I/O port (type template = "p") - nil
*WARNING* (TE-1308): Failed to perform syntax check for cellview 'CIS_v0 veri functional'.
*WARNING* (TE-1312): Compilation errors or warnings have been detected in the HDL file for cellview 'CIS_v0 veri functional'. To view the parse log for details, choose 'Parser Log File' from the 'View' menu.
*WARNING* (TE-4309): Extract failed for cellview 'CIS_v0 veri functional'

Looking for your kind suggestions..

OK, I was talking about checking the "xrun -version" in the UNIX terminal window that you started Virtuoso from. The symptoms sort of look like that - check also "which ncvhdl" in that terminal window. For me, I get a popup saying it can't be found in my path.

The code above compiles OK though if I do have the software set up correctly.

If you can't get this working, I suggest contacting customer support - this should be easy enough to resolve with an application engineer being able to look at your setup.

Andrew

OK, I was talking about checking the "xrun -version" in the UNIX terminal window that you started Virtuoso from. The symptoms sort of look like that - check also "which ncvhdl" in that terminal window. For me, I get a popup saying it can't be found in my path.

The code above compiles OK though if I do have the software set up correctly.

If you can't get this working, I suggest contacting customer support - this should be easy enough to resolve with an application engineer being able to look at your setup.

Andrew

Error* _gets: argument #1 should be an I/O port (type template = "p") - nil : this error i got resolved, as i earlier do not have root access to the editor.

Please confirm : AMS is required for working with cellview created with verilog code, as spectre can only handle analog simulation not digital one?