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synthesizing Verilog code in Cadence Virtuoso

Hello,

I would like to ask you how I can synthesize a logic gate from my Verilog RTL description. For example, I have made a simple 4-bit counter in Verilog and I have tested the functionality with the AMS simulation, it is working fine but now I want to translate this code to logic gate in Cadence Virtuoso and do the layout of it.

I am using Cadence Virtuoso version 6.1.8-64b

Thank you in advance

Regards

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Saloni Chhabra over 3 years ago

Hi,

RTL to gate-level netlist conversion is done using our synthesis tool called Genus. You can't do this in Virtuoso.

Regards,

Saloni
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Senan over 3 years ago in reply to Saloni Chhabra

Dear Saloni

Thank you very much for your answer

Regards
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Senan over 3 years ago in reply to Saloni Chhabra

Dear Saloni

Thank you very much for your answer

Regards
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