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datapoints/memory array

Omar Ghazal

HI everyone

I have two questions here

first: how to convert a set of datapoints (stored in a text file) each having ten bits (b0.....b9) to be the input trigger of ten pulses sources (V0..V9) with timing between reading each datapoint 30 ns..See the photo plz

Second : I am working on designing a memory array if I have one cell (1bit ) designed and now I want to verify that it can be work as an array of 1Mbit (1024 bits) So how can I multiply the design in an array of 1024 because its hard to make all these connection . Any ideas.

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  • ShawnLogan

    Dear Omar Ghazal,

    Omar Ghazal said:
    how to convert a set of datapoints (stored in a text file) each having ten bits (b0.....b9) to be the input trigger of ten pulses sources (V0..V9) with timing between reading each datapoint 30 ns..See the photo plz

    If I understand your question, you would like to create a subcircuit that can read a 10 bit bus contained in a test file and apply each bit as the input to 10 pulse generators. If so, I put together an example of a subcircuit implemented in veriloga. I placed a note with the test bench I assembled at URL:

    https://www.dropbox.com/s/7jix0i0d1efmgdz/omar_10bit_bus_example_sml_081722v1p0.pdf?dl=0

    The note also includes the veriloga source code, test bench variables, outputs, and example waveforms. Your input data file does not contain any delimiters - which with my limited skills in veriloga, makes the coding difficult as veriloga does not have a lot of functions to parse a string by character by character without a delimiter. Hence, I wrote a UNIX script to do the conversion to a "csv" file and have included that script. It takes as its input your text file with no delimiters between bits and creates a ".csv" version with a comma delimiter between bits. This file is placed in your working directory and modify the veriloga code to use the full path to this file in lieu of the path I used for the file.

    The veriloga and UNIX script are attached if they are useful to you. I had to change to file extensions to ".txt" to upload them.

    Omar Ghazal said:
    I am working on designing a memory array if I have one cell (1bit ) designed and now I want to verify that it can be work as an array of 1Mbit (1024 bits) So how can I multiply the design in an array of 1024 because its hard to make all these connection . Any ideas.

    To be honest, you have not provided me, anyway, enough information with regard to the specific memory topology you are trying to create and what inputs to the cells are common to provide any helpful ideas, Sorry.

    Shawn

    Fullscreen 5430.convert_to_csv.txt Download 
    #!/bin/ksh

if [ $# -ne 1 ]; then
    echo "Usage: convert_to_csv < filename> "
    exit 127
fi

cp -p $1 tempfile0

sed '1,$s/00/0,0/g' tempfile0 > tempfile1
sed '1,$s/11/1,1/g' tempfile1 > tempfile0
sed '1,$s/01/0,1/g' tempfile0 > tempfile1
sed '1,$s/10/1,0/g' tempfile1 > tempfile0

sed '1,$s/00/0,0/g' tempfile0 > tempfile1
sed '1,$s/11/1,1/g' tempfile1 > tempfile0
sed '1,$s/01/0,1/g' tempfile0 > tempfile1
sed '1,$s/10/1,0/g' tempfile1 > tempfile0

mv tempfile0 $1.csv
rm tempfile1

echo "Completed! Output file is \"$1.csv\"."

    Fullscreen 5430.veriloga.txt Download 
    // VerilogA for sdd5e_TB, ten_bit_word_gen_triggered, veriloga

// Crude code to provide example of subcircuit to read 10 bit bus from file
// and provide subsequent 10-bit output on rising edge of input clkin
// Missing many features and insufficient file checking...but works..
// sml 8/17/2022 v1.0

`include "constants.vams"
`include "disciplines.vams"

module ten_bit_word_gen_triggered(v0,v1,v2,v3,v4,v5,v6,v7,v8,v9,clkin);
input clkin;
output v0,v1,v2,v3,v4,v5,v6,v7,v8,v9;
electrical v0,v1,v2,v3,v4,v5,v6,v7,v8,v9,clkin;

integer file;
integer count, count0,count1,count2,count3,count4,count5,count6,count7,count8,count9;
integer input_string;

real tdelay, trise, tfall, vthreshold;
real val0, val1, val2, val3, val4, val5, val6, val7,val8,val9;
real v0_int,v1_int,v2_int,v3_int,v4_int,v5_int,v6_int,v7_int,v8_int,v9_int;

analog begin
     @(initial_step) begin
         count0 = 0;
         count1 = 0;
         count2 = 0;
         count3 = 0;
         count4 = 0;
         count5 = 0;
         count6 = 0;
         count7 = 0;
         count8 = 0;
         count9 = 0;
         tdelay = 0;
         trise = 100e-12;
         tfall = 100e-12;
         vthreshold = 0.50;

                                  
        file = $fopen("/project/sdd5e/users/smlogan/cds/omar_10bit_bus_example.txt.csv", "r");
                               
        if ( $fscanf(file, "%f,%f,%f,%f,%f,%f,%f,%f,%f,%f",val0,val1,val2,val3,val4,val5,val6,val7,val8,val9 ) == 10 ) begin                                                     
           count0 = val0;
           count1 = val1;
           count2 = val2;
           count3 = val3;
           count4 = val4;
           count5 = val5;
           count6 = val6;
           count7 = val7;
           count8 = val8;
           count9 = val9;         
         end
            v0_int = val0;
            v1_int = val1;
            v2_int = val2;
            v3_int = val3;
            v4_int = val4;
            v5_int = val5;
            v6_int = val6;
            v7_int = val7;
            v8_int = val8;
            v9_int = val9;
   end

@ cross(V(clkin)-vthreshold, +1) begin

        count0 = 0;
        count1 = 0;
        count2 = 0;
        count3 = 0;
        count4 = 0;
        count5 = 0;
        count6 = 0;
        count7 = 0;
        count8 = 0;
        count9 = 0;
        trise = 100e-12;
        tfall = 100e-12;
        vthreshold = 0.50;

     if ( $fscanf(file, "%f,%f,%f,%f,%f,%f,%f,%f,%f,%f",val0,val1,val2,val3,val4,val5,val6,val7,val8,val9 ) == 10 ) begin                                                     
        count0 = val0;
        count1 = val1;
        count2 = val2;
        count3 = val3;
        count4 = val4;
        count5 = val5;
        count6 = val6;
        count7 = val7; 
        count8 = val8;
        count9 = val9;        
      end
         v0_int = val0;
         v1_int = val1;
         v2_int = val2;
         v3_int = val3;
         v4_int = val4;
         v5_int = val5;
         v6_int = val6;
         v7_int = val7;
         v8_int = val8;
         v9_int = val9;
end
   V(v0) <+transition(v0_int, tdelay, trise, tfall);                                       
   V(v1) <+transition(v1_int, tdelay, trise, tfall); 
   V(v2) <+transition(v2_int, tdelay, trise, tfall);
   V(v3) <+transition(v3_int, tdelay, trise, tfall);
   V(v4) <+transition(v4_int, tdelay, trise, tfall);
   V(v5) <+transition(v5_int, tdelay, trise, tfall);
   V(v6) <+transition(v6_int, tdelay, trise, tfall);
   V(v7) <+transition(v7_int, tdelay, trise, tfall);
   V(v8) <+transition(v8_int, tdelay, trise, tfall);
   V(v9) <+transition(v9_int, tdelay, trise, tfall);

$fclose( file );
end
                        
endmodule

  • Omar Ghazal
    in reply to ShawnLogan

    Thanks  that's really helpful

  • ShawnLogan
    in reply to Omar Ghazal

    Dear Omar,

    Wonderful - that is all that matters! My pleasure and good luck! Thank you for letting us know!

    Shawn

Reply
  • ShawnLogan
    in reply to Omar Ghazal

    Dear Omar,

    Wonderful - that is all that matters! My pleasure and good luck! Thank you for letting us know!

    Shawn

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