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programable pattern generator

hdeshmukhnvidia

I wanted to check if some one has written a verilogA model for a patter generator, we are trying to develop a verilogA block which can generate NRZ, Clock, PAM4 pattern, take input from a file and also has option to generate a prbs sequence , if some one as design something please share 

  • I don't have an example Verilog-A module to do this (maybe somebody else does), but much of this can be done with the built-in vsource component in spectre, either picking the type as pulse, bit or prbs. That can handle the clock, NRZ and PAM4, with the PRBS sequence controls. If you want the pattern defined in a file, you could create a file with spectre pattern statements (see "spectre -h pattern") with a .scs suffix and then include it as a model file or definition file in ADE, and then your bit source can reference the pattern name (note that patterns can be nested for complex patterns).

    Regards,

    Andrew

  • in reply to Andrew Beckett

    Dear hdeshmukhnvidia,

    In addition to Andrew's good suggestion, there was a recent Forum post where I provided a veriloga based pattern generator whose values are read from a comma-separated variable file. I included the code and examples of its use. This may or may not be of use to you, but I thought I might add the comment. The Forum post that contains the note and code is at URL:

    https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/52283/datapoints-memory-array

    I hope between Andrew's suggestion and the information in this note, you will be able to proceed!

    Shawn

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