How to make use of the symbol_noconn for dangling verilog bus ports without shorting them ?

Hello,

I've a setup according to https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nZGd&pageName=ArticleContent , but for an intermediate Verilog netlist written out by Innovus, the generated fast schematic results in a bus being shorted in the schematic. The bus outputs of one instantiated module are not used in the instantiation - these are dangling.

The import is run with IC 6.1.8-500ISR13, verilog import with "fast" option ON (connection-by-name).

Is there any additional switch or option required to receive a schematic without shorted bus by the net <*4>netNoConn0  - as this shorts the bus data_o of the instantiated module master_test ?

The simple verilog netlist uses connection-by-name, there are some ports dangling (I removed the parts which are not relevant):

module master_test (in_i,test_o,data_i,data_o,test_o,test_chain_o,VDD,VSS);

output [3:0] data_o;

(...)

endmodule

module top_test (in_i,data_i,data_o,VDDM1,VSSM1);

(...)

master_test test_u (.in_i(in_i),.data_i(data_i),.VDD(VDDM1),.VSS(VSSM1));

(...)

endmodule

Any idea ?

Thanks a lot in advance.