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Difference between Transient and Transient+Noise simulation

Senan

Hello

I would like to ask about the difference between "Transient" and "Transient+Noise" simulation in Cadence Virtuoso.

For me I was thinking that what ever I get from running the transient simulation is what really I can see at my circuit output in time domain including noise, offset or any kind of disturbance,

But looking to have "Transient+Noise" makes me thinking that perhaps Virtuoso will only consider the noise contribution (Models) when we select this type of simulation.

Please I need your help for running the Transient+Noise setup

Thank you in advance

Best Regards

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  • in reply to Frank Wiedmann

    Thank you Frank and Shawn for your helpful answers and comments,

    I will study your comments  and resources before addressing the next question

    Thank you once again

    Best Regards

  • in reply to Senan

    Hello once again,

    Actually what puzzled me after receiving our chip prototype from foundry is the alternative drop in the supply voltage due to the switching activity of the circuits in our chip.

    I admit that supply line disturbance is expected practically due to switching currents that develop a voltage drop on the supply output resistance. However, I am using LAB supply voltage where I am surprised to see him suffer like this, it is not simple LDO circuit.

    What I need to conclude, using an ideal voltage source is not the right when simulating Mixed-signal IC with Cadence (or any other type of simulation), for example, I have the same simulation setup of the measurement and I see that switching activity has zero effect on the supply voltage (ideal voltage source)

    Since I want to learn from my practical results and to make a more realistic simulation with Cadence in the future, I would ask for you suggestion for using the ideal voltage supply in the circuit simulation, like do I need to connect a small resistor in series to represent the output resistance.

    Thank you

    Best Regards

  • in reply to Senan

    Dear Senan,

    Senan said:

    Actually what puzzled me after receiving our chip prototype from foundry is the alternative drop in the supply voltage due to the switching activity of the circuits in our chip.

    What do you mean when you state "alternative drop"? Are you describing a measured DC voltage at the supply pin (or pins) relative to the measured power supply at the power supply pins? Are you measuring the voltage drop between the pins of your power supply and an internal voltage within your IC? Figure 1 shows a conceptual diagram of a power distribution network, and I am not sure what nodes and measurement you are referring to.

    Senan said:
    I have the same simulation setup of the measurement and I see that switching activity has zero effect on the supply voltage (ideal voltage source)

    Is your netlist composed of a schematic or layout based (extracted view) of your subcircuit or IC? If an extracted view based netlist, is your extracted view a C only or RC based extracted view. Are there sufficient pins on your layout to properly represent its power and ground plane? A common problem is that only one or two pins are included for the supply and ground pins and all the subcircuit/IC current is forced to run through only a via or two which results in an excessive voltage drop not representative of the actual circuit.

    Senan said:
    Since I want to learn from my practical results and to make a more realistic simulation with Cadence in the future, I would ask for you suggestion for using the ideal voltage supply in the circuit simulation, like do I need to connect a small resistor in series to represent the output resistance.

    The best solution from the perspective of accurately estimating the voltage drops and switching noise is to use an RC based extracted view of your subciruit or IC where the layout of the supply and ground planes are included in the layout. Sufficient pins in the supply and ground planes should be included in the layout to reflect how they are actually connected. Tools exist to compute IR drops of a layout given an estimate of subcircuit currents from even a schematic view based simulation that are quite accurate. 

    Using just a small resistor in the supply and ground nodes is probably a bit too simplistic as the supply and ground distribution networks are more complex as shown in Figure 1.

    I hope I understood your question enough to provide some helpful thoughts Senan. Let me know if I totally misunderstood your questions if I did.

    Shawn

    Figure 1

  • in reply to ShawnLogan

    Dear Shaun,

    Thank you very much for your nice explanation and great effort you kept in your reply,

    I am actually and always do the post layout simulation in my comparison to my real measurement with RC extraction type.

    I mean by the "alternative srop", because the noise coupled to the DC source is AC, hence I mean alternative.

    I am measuring this disturbance at the IC supply pins of VDD and GND since I have no possibility to make internal IC probing because our chip is completely covered with a protection layer, I have no access to the IC internal nodes. So what I am doing is putting the oscilloscope probe at the VDD pin of the IC and monitoring its output, which shows the large amplitude noise coupled (like 700m Vpp). 

    May be I am wrong, but I found it mysterious to see a noise coupled to the supply lines when I am using LAB power supply with thick probes. If I see this disturbance inside the chip then I can blame my chip power rings.

    With regards to the number of pins, I used 3 pairs of VDD and GND to power the chip, and they are evenly distributed around the chip. The number of via are carefully and generously provided to avoid this bottle nick. 

    I have used thick metal in the power ring to reduce the IR drop.

    It looks from you nice explanation that I might have IR drop which I need to simulate using special tools which I have not used actually.

    Indeed what I always do is when I run the post-layout simulation, I print the DC voltage at a different place on the supply rails to monitor the drops for tracking the IR drop. If I am not happy with the IR then I usually increase the with of the rails metal width and using two layers at least one above the other when the width becomes excessive.

    Thank you once again

    Best Regards

  • in reply to Senan

    Dear Senan,

    Thank you for clarifying your term "alternative drop"! II now understand it is a peak-to-peak measurement of the apparent noise observed at the VDD and GND pins of your IC. I also found the details of the netlist you used in simulation, your layout methodology, and the measurement extremely helpful!

    I've had a lot of lab experience and can try to suggest a few items to consider if you are interested.

    1. Are you using a high-impedance probe or a 50 ohm probe. A high impedance probe will be very susceptible to EM and may show both the measurement and radiated noise- you cannot separate the two. Using a 50 ohm probe minimizes any radiative coupling.

    2, 3. Chip topology and internal bypass - see comment 2 in Figure 1.

    4. Where, what type, and how much external bypass is there between VDD and VSS?

    5. Are you observing he 700 mVpp "AC noise" on both the VDD and GND pins with your probe? Or is the 700 mVpp "AC noise" measurement between the VDD and GND pins? In other words, referring to Figure 1, which of the 4 measurement configurations are you using to take your measurements?

    My first guess is that the 700 mVpp measurement you are observing is an artifact of the measurement. With that much noise on presumably a 1 V DC supply voltage would cause massive circuit failure. If your measurement configuration was not exactly between the VDD and VSS pins, then the measured noise may be considered a common-mode noise element - still far too high - but it may explain why your circuit is still functioning.

    I hope I fully understood your answers to my first question and these thoughts are somewhat relevant and maybe even useful to you Senan!

    Shawn

    Figure 1


  • in reply to ShawnLogan

    Hello Shaun,

    I am deeply grateful for your explanation and the much of help and suggestions that takes you an effort to tackle our problem.

    I will answer your question one by one:

    1. I am using the 50 Ohm probe for measuring the supply noise, and for our chip circuit we used the 1 M ohms because our circuit, in particular, the amplifier prototype is not designed to drive a heavy load like 50 Ohm.

    2.3.  We distributed several bypass capacitors at the time of our chip design, but you know the range can not be more than tens of pico farad due to the die size constraint.

    4. Yes we connected bypass capacitors on our PCB board near to the supply, ground pins. We used a combination of 10 µF Electrolytic capacitor time plus 100 nF Ceramic type capacitor.

    5. We are measuring the noise like measurement configuration number 1

    6. Our package type is PGA 100 (Ceramic Pin Grid Array), one thing might be useful to mention, our chip area is small as compared to the package cavity but we used this type of package because we need 100 pins. As a consequence, the bonding wires are lonf to the maximum length allowed for packaging. 

    Actually, the bonding wires was not considered by our simulation with its inductance, capacitance and resistance effect that also give an answer to the difference between out simulation in Cadence and the practical measurements we are observing. The highest level of simulation we performed is by including the pad frame. Even we are not aware if there is a simulation possibility that includes the package/bonding leads effect and could be interesting to know.

    I would like to share with you a snap screen from the oscilloscope measurement of the fully differential amplifier circuit. In this setup the amplifier both inputs are tied to the mild supply voltage, the same for the common mode voltage of 1.65 V where we use VDD=3.3 V.

    Ideally the differential outputs should be equal to VCM= 1.65 V as also proved by simulation, in addition to differential offset, however we set the closed loop gain to unity so th offset voltage should not be effective.

    When you look to the output you see the noise coupled at one of the outputs, Vout+ and also the noise coupled to VCM and VDD rails. Note that VDD and VCM are both provided directly from the power supply.

    I believe that noise should be random but what we see is deterministic noise looks like oscillation. On the other hand, we could use the ircuit to amplify by varying the gain level and also the SNR becomes better with higher signal amplitude, which means that if the circuit is still working as a linear amplifier cause if the circuit is not stable/oscillating it can not be used linearly.

    I am apologizing if I made the post lengthy and thank you once again for your kind help

    Regads

  • in reply to Senan

    Dear Senan,

    Thank you for your information - it was most informative and provides some good clues as to a possible hypothesis as to the origin of your noise! I've responded to your answers and follow with a couple of items to consider if you have the time and patience!

    Senan said:
    1. I am using the 50 Ohm probe for measuring the supply noise, and for our chip circuit we used the 1 M ohms because our circuit, in particular, the amplifier prototype is not designed to drive a heavy load like 50 Ohm.

    Excellent. The use a 50 ohm probe for measuring the supply is your best choice.

    Senan said:
    2.3.  We distributed several bypass capacitors at the time of our chip design, but you know the range can not be more than tens of pico farad due to the die size constraint.

    This is very good information Senan. You are correct that the amount of internal bypass is limited by area constraints. However, it is essential to both include it in your layout and simulations as I think you will also conclude after my next set of comments.

    Senan said:
    4. Yes we connected bypass capacitors on our PCB board near to the supply, ground pins. We used a combination of 10 µF Electrolytic capacitor time plus 100 nF Ceramic type capacitor.

    The 100 nF ceramics should help - but only up their self-resonant frequency. Depending on the physical size of your chip capacitor, their internal self-inductance will limit their use as a bypass element. For a 100 nF (0.10 uF), this is an example of their limited bypass frequency range of abut 20 MHz:

    reference: Parasitic Inductance of Multilayer Ceramic Capacitors Jeffrey Cain, Ph.D. AVX Corporation

    Senan said:
    5. We are measuring the noise like measurement configuration number 1

    Excellent!

    Senan said:

    6. Our package type is PGA 100 (Ceramic Pin Grid Array), one thing might be useful to mention, our chip area is small as compared to the package cavity but we used this type of package because we need 100 pins. As a consequence, the bonding wires are lonf to the maximum length allowed for packaging. 

    Actually, the bonding wires was not considered by our simulation with its inductance, capacitance and resistance effect that also give an answer to the difference between out simulation in Cadence and the practical measurements we are observing. The highest level of simulation we performed is by including the pad frame. Even we are not aware if there is a simulation possibility that includes the package/bonding leads effect and could be interesting to know.

    Unfortunately, the inductance of bond wires is quite significant and I think you might consider including its impact in your netlist and simulations. Both the mutual and self-inductances of a bondwire can impact high frequency performance. Intuitively, the presence of the bond wire acts as a filter with your on-chip capacitance. In the example I show below with a 50 pF internal bypass and a 5 nH wire bond inductance, the on-chip power impedance is inductive above 800 MHz - which is clearly not what your internal circuit was simulated with. Further, any amount of external bypass capacitance cannot reduce the impact of that wirebond inductance.

    In addition, there is mutual coupling between adjacent bondwires, which may also lead to coupling between undesired nodes (such as an output node and a power node). The best you can do is to both model and attempt to minimize the impact of the bondwire inductance through internal bypass a package design.

    You noted your chip is small relative to the cavity of the package in which it was placed. Is there any chance you can fit a small single layer ceramic capacitor (e.g. from Johanson) in the package and place multiple wirebonds to it and the chip VDD pads? In work I did many years ago, I was able to significantly reduce the impact of wirebond lead inductance using this methodology.

    In trying to study your waveforms closely, it appears the frequency of your apparent oscillation is at about 6.5 MHz on both the supply, common-mode, and output waveforms. I am wondering if the presence of the package inductance is leading to a parasitic low level oscillation due to mutual coupling or the impedance of the internal supply coupled with your transient currents. If you expand the timescale, can you view any higher frequency oscillations superimposed over the 6.5 MHz?

    You might also try varying the supply voltage and temperature/load to reduce the supply current to its lowest possible value to see if the amount or frequency of the apparent noise is changed.

    A lot of words...but hope this helps provide an idea or two Senan.

    Shawn

  • in reply to ShawnLogan

    Dear Shawn,

    I am very grateful for your help and the valuable comments you advised me to do, 

    I would like to give you a feedback on it, first of all we were not allowd to put the internal capacitor in the chip like you suggested, rather we made new PCBs and located the capacitors near to the VDD, GND pins. We optimized the power routing as well with PCB ground plate. As a result the noise is largely reduced. 

    However, the reality behind the large anplitude of the signal I shared before was in a noise, we dicovered that our amplifier was not too much stable and those are oscillating signals.

    Back to the noise improvement, we have foundout new thing that might be another reason for noise contribution, during the design package, we did not connect the chip substrate to the package cavity. In some design I have explored, I found that  people are using epoxy conductive glue to attach the die to the package cavity then they routed to a ground pin or sometimes to the available extra pin of the package. So we have unfortunately missed this, and I would like to ask from your experience how big is important this step.

    Thank you once again for your kind help and I wish you in advance a happy new year full of health and success.

    Best Regards

  • in reply to Senan

    Dear Senan,

    First things first - thank you very much for your update!

    Senan said:
    irst of all we were not allowd to put the internal capacitor in the chip like you suggested, rather we made new PCBs and located the capacitors near to the VDD, GND pins. We optimized the power routing as well with PCB ground plate. As a result the noise is largely reduced. 

    Excellent! I understand your constraints as fitting an internal bypass can be both a physical challenge and an expense. You were wise to explore other alternatives.Optimizing the power grid routing and using a ground plane are very good practices. In particular, the ground inductance provided by the ground plane should be much less than that provided by one or more traces to a pin.

    Senan said:
    However, the reality behind the large anplitude of the signal I shared before was in a noise, we dicovered that our amplifier was not too much stable and those are oscillating signals.

    This also makes sense and was one of the items I commented on based on your waveforms and observations. Although perhaps not good news, at least you have identified it as a contributor - good work Senan!

    Senan said:
    Back to the noise improvement, we have foundout new thing that might be another reason for noise contribution, during the design package, we did not connect the chip substrate to the package cavity. In some design I have explored, I found that  people are using epoxy conductive glue to attach the die to the package cavity then they routed to a ground pin or sometimes to the available extra pin of the package. So we have unfortunately missed this, and I would like to ask from your experience how big is important this step.

    It turns out, I do have some experience with the use of both conductive and non-conductive epoxies for chip attach. In the case I am referring to, there was a single sustaining amplifier placed in a ceramic package with a piece of quartz to form an oscillator that served as a timing reference. For some timing reference frequencies, I observed non-quartz related oscillations. I studied the use of a silver based conductive and non-conductive epoxies to secure the substrate of the silicon sustaining amplifier to the internal gold-plated ground plane. The internal ground plan connected to the package pins with additional gold plating - there were no wire bond connections from the internal ground plane to the package pins. If I recall (as it was some time ago), there was a slight difference in the frequency and magnitude of the parasitic oscillation, but the use of a conductive or non-conductive epoxy did not make a tremendous difference. However - the silicon device did have contacts from the substrate to its top level metal. Hence, the substrate was still electrically connected to ground through top level metal and its lossy vias. I do not know if your substrate is connected to top level metal. If it is not, then I think you should definitely consider using conductive epoxy and connect the surface to which the epoxy is connected to ground - even if it is with wire bonds.

    A second item to consider, which I did not explore, was latch-up. The probability of latch-up is far greater and will be more pronounced on a device whose substrate is floating (as will its ESD robustness). Hence, in our case, we did choose to use conductive epoxy in lieu of a non-conductive epoxy for chip attach.

    I hope my recollection provides some thoughts to consider Senan!

    Shawn

  • in reply to ShawnLogan

    Dear Sawn,

    I am happy to tell you that with your nice help, our test with regard to the noise is largely improved

    Thanks a lot for your patience and kind help

    Best regards

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