VCO phase noise modeling using a transient noise simulation

Dear asrf,

asrf said:

however when I run transient noise simulation and use PSD calculator I dont get a proper result

Achieving reasonable correlation in phase noise between a transient noise simulation and pss/pnoise simulation is absolutely possible. However, it requires a significant amount of care in your choice of transient noise simulation settings, PSD analysis, and pss/pnoise simulator settings. The amount of information your Forum post provides does not include enough for me to give you concrete suggestions as your PSD GUI settings are not relevant without knowing the details of your transient noise and pss/pnoise analysis.

However, I might suggest you study a similar question and the notes I assembled for each in the Forum posts at URL:

https://community.cadence.com/cadence_technology_forums/f/rf-design/51484/comparing-transient-noise-pnoise-and-pnoise-with-lorentian-approximation-of-a-ring-oscillator

There is a link to a set of notes that details considerations for comparing phase noise results for a transient noise simulation and pss/pnoise simulations.

https://www.dropbox.com/s/5zalilay6sqa06b/phase_noise_response_081422v1p0.pdf?dl=0 

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/51696/snr-calculation-wrong-by-3-db/1383427?focus=true

There is a link in this post to a set of notes describing some subtleties of using the Spectrum Assistant it produce PSD results from a transient noise simulation and a means to set your transient noise simulation parameters to produce valid Spectrum Assistant PSD results.

Shawn

Thank you for your time and effort.

These are my transient noise simulation setup

Thank you for the links you have provided. I will study them.

Some of these links are about phase noise. Here I am basically looking at voltage noise. (or integrated voltage noise)

I am not running pss/pnoise since my circuit has verilogA code and it does not work. 

I use noise simulation to check Vnoise of diode connected transistor

Dear asrf,

asrf said:

Some of these links are about phase noise. Here I am basically looking at voltage noise. (or integrated voltage noise)

I am not running pss/pnoise since my circuit has verilogA code and it does not work. 

I use noise simulation to check Vnoise of diode connected transistor

I thought your goal was to :

asrf said:

model VCO phase noise

and hence included the phase noise information. I understand your initial simulation efforts are aimed at correlating the small-signal AC noise results with those using the Spectral Assistant after a transient noise simulation. That is why I included the link to the second Forum post. Starting on page 15 of the dropbox link in the second Forum post,

https://www.dropbox.com/s/7vxzliml4uz6518/psd_study_sml_090622v1p0.pdf?d|=0 

I compare the transient noise simulation results with the AC small signal noise results for 4550 ohm resistor with and without a bandlimiting 100 fF capacitor. I illustrate the impact of one's choice of noisefmax and sampling time on the integrated noise results. With the proper choice of noisefmax, sampling time, and integration step size, the small signal and transient noise/PSD results correlate quite well. From page 18 of the note, shown below as Figure 1, the data suggests the transient noise and AC small signal noise integrated values correlate well as long as the sample rate is chosen to be higher than the value of noisefmax.

Looking at your transient noise simulation parameters, I note you have set noisefmax to 10 GHz. However, you have set the sample rate to 2.50 GHz. Hence, you will experience aliasing of noise components above 1.25 GHz into the lower frequency range and as also shown in Figure 1, the average PSD noise will be increased beyond its expected value.

Inspecting the transient noise PSD noise results you show in your Forum post, the values appear much greater than those for your small signal noise results - which is consistent with the presence of aliasing.

Further, inspecting your Spectral Assistant parameter "Peak Saturation level" in your initial Forum posts indicates you selected its value as 0. Hence, all measurements are expressed with respect to an rms level of 707 mV - not 1 V. If you are not familiar with the "Peak Saturation Level" parameter, you might want to review it using the Cadence help function or the manual. I outline its function in Figure 2 from a second note referenced in the Forum post:

I hope this helps clarify my comments and included references asrf and is somewhat useful to you!

Shawn

Figure 1

(from page 18 of https://www.dropbox.com/s/7vxzliml4uz6518/psd_study_sml_090622v1p0.pdf?d|=0   )

Figure 2

(from page 15 of link in Forum post: community.cadence.com/.../1383427

Thanks alot.

Yes I studied this document its very helpful. I really appreciate it.

Yes my Fs is 2.5GHz and Fmax is 10G so I have aliasing. In my new simulation I am planning to reduce my steps to

40p so I have 25GHz sampling rate and then Fs/2 = Fmax so I set Fmax to be 12.5GHz.

--------------------------------------------------------------------------------

One of the issues of this simulation is:

since I want to observe flicker noise my resolution BW should be at least 1KHz and for this I need 1mS simulation time.

So this simulation will take very long time.

Is this the typical way of simulating PLL ? lets say each time we need to change any parameter within loop we need to wait hours or half a day for simulation ?

Dear asrf,

If I understand your concerns, I've added a few comments. I hope I understood them correctly and apologize, in advance, if I have not!

asrf said:

since I want to observe flicker noise my resolution BW should be at least 1KHz and for this I need 1mS simulation time.

So this simulation will take very long time.

If you are using any modern MOS technology, the 1/f noise component extends to a phase noise offset frequency of much, much greater than 1 kHz. Hence, unless you have a specific interest in the 1/f noise at 1 kHz, there is no need to choose a simulation time that will allow a Fourier analysis of frequency components as low as 1 kHz. Typically 1/f noise corner for a submicron CMOS technology extend to 1 - 100 MHz.

asrf said:

Is this the typical way of simulating PLL ? lets say each time we need to change any parameter within loop we need to wait hours or half a day for simulation ?

I might suggest you consider the application of your VCO when used in the PLL you mention for two reasons.

1. Recall that the phase noise of the PLL output will ideally reflect the phase noise of the input reference signal - and NOT the phase noise its inherent VCO - for frequencies up to the PLL loop bandwidth. My guess is your PLL bandwidth is far greater than 1 kHz. Hence, the phase noise of the VCO at 1 kHz will be attenuated signficantly by the PLL open loop gain at 1 kHz.

2. What is the application for the output clock of your PLL? If it is the source clock to some type of standard, there is usually a jitter requirement on the clock that is specified over some frequency range. For example, in telecommunications, a commonly used set of of offset frequencies used in its specification is between 12 kHz and 20 MHz. Hence, a filtering operation is performed on the PLL output clock using a bandpass filter between 12 kHz and 20 MHz. This will further attenuate any phase noise with components as low as 1 kHz.  Therefore, it might be worth studying the end application of your PLL to better understand what frequency range your VCO phase noise simulations must include.

Shawn

Hi 

Thank you for your time. I appreciate your time and effort

"Recall that the phase noise of the PLL output will ideally reflect the phase noise of the input reference signal - and NOT the phase noise its inherent VCO - for frequencies up to the PLL loop bandwidth"

yes for low offsets its M^2 * reference PN (M= division ratio)

"This will further attenuate any phase noise with components as low as 1 kHz.  Therefore, it might be worth studying the end application of your PLL to better understand what frequency range your VCO phase noise simulations must include."

Its true I might not need to have ResBW below 1KHz

Recently in 5G applications phase noise is integrated from 1KHz to 100MHz

We can increase our steps to reduce sample frequency and also reduce FNOISE_MAX (For example 1GHz) BUT! the problem is if we have a PLL operating at 5GHz in order to run transient we need to have sampling freq at least at 10GHz right ? I would make my Fs =50GHz so then we will have high Fs/2 and high FNOISE_MAX again and in order to obtain 1KHz ResBW we need to have (1m * 50G)+1 samples !

-------------------------------------------------------------------------------

I was able to plot the PSD of simple noise source finally:

It was not easy. I also took moving average to make it smooth.

I made Fs/2 = FNOISE_MAX but I know for the best results FS/2 should be higher than 2*FNOISE_MAX

>>>>>> Also I have learned that its better to run multiple sims and take average (at least 3)

Dear asrf,

From what I read, it seems to me you are making very good progress! Great!  Please allow me to provide a note or two in response to your added comments.

asrf said:

Its true I might not need to have ResBW below 1KHz

Recently in 5G applications phase noise is integrated from 1KHz to 100MHz

 

We can increase our steps to reduce sample frequency and also reduce FNOISE_MAX (For example 1GHz) BUT! the problem is if we have a PLL operating at 5GHz in order to run transient we need to have sampling freq at least at 10GHz right ? I would make my Fs =50GHz so then we will have high Fs/2 and high FNOISE_MAX again and in order to obtain 1KHz ResBW we need to have (1m * 50G)+1 samples !

However, in a 5G based synthesizer the phase-locked loop bandwidth will in general far exceed 1 kHz. From a recent paper whose reference is shown in [1], an optimum bandwidth of about 1 MHz is proposed as a trade-off between loop transient response and phase noise.Therefore, it seems feasible to be concerned with phase noise components over 10K or 100K in your PLL simulation. At these offset frequencies, you will just start to see the influence of the phase noise of its VCO on the PLL output phase noise. In a separate calculation, you can include the phase noise of your reference clock. I do not think it is feasible to simulate the phase noise of an entire PLL with a high frequency (GHz) VCO at the circuit level to establish its phase noise at an offset frequency of 1 kHz.

asrf said:

I made Fs/2 = FNOISE_MAX but I know for the best results FS/2 should be higher than 2*FNOISE_MAX

I agree.

asrf said:

>>>>>> Also I have learned that its better to run multiple sims and take average (at least 3)

If you can afford the simulation time, that is fine. However, as a side note, this "averaging" can also be provided inherently in a power spectral density computation.

Shawn

[1] Z. Berber and S. Kameche, "Influence of Loop Bandwidth Parameter on Integer PLL Frequency Synthesizer Performances in 80 GHz mm-Wave 5G Frequency Band," 2018 IEEE/ACS 15th International Conference on Computer Systems and Applications (AICCSA), 2018, pp. 1-2, doi: 10.1109/AICCSA.2018.8612879.

I tried to compare transient noise with NOISE simulation

Results are not satisfying. Although my BW resolution is around 700Hz data below 1e5 Hz is off

Moving average makes data precise at high freq (>1MHz) however, it introduces error at lower offsets.

I tried to compare transient noise with NOISE simulation

Results are not satisfying. Although my BW resolution is around 700Hz data below 1e5 Hz is off

Moving average makes data precise at high freq (>1MHz) however, it introduces error at lower offsets.

Dear asrf,

asrf said:

Results are not satisfying. Although my BW resolution is around 700Hz data below 1e5 Hz is off

Your curve labeled "noise sim" does not appear to be the actual simulation data. It would be be best to superimpose the actual small-signal noise simulation over your transient noise PSD results. Nevertheless, even if the curve labeled "noise sim" accurately reflects the small-signal noise result, the yellow PSD results appears to be a reasonable representation of the small-signal results. The difference between the yellow and blue data at frequencies over 7 or 8 GHz is due to your choice of a 10 GHz noisefmax.

The differences at low frequency, in my mind, are easily explained by the very few frequency points available for the low frequency range of the curve and the statistical error.

A transient noise is a statistical simulation and hence there are bounds on the degree to which a single simulation provides a good statistical estimate of the actual random noise. In essence, your transient simulation uses a single seed to the random noise included in the simulation. Suppose you re-ran the simulation using a different seed? There will be some difference between the two PSD simulation results - neither is "wrong" but just illustrate the statistical variation.

As a result, Cadence recommends repeating a transient noise analysis to get an estimate of the statistical error. There is an option to run multiple transient noise simulations within the Transient Noise GUI - or you can simply repeat them with different seeds.

asrf said:

Moving average makes data precise at high freq (>1MHz) however, it introduces error at lower offsets.

I do not recommend using a moving average function over frequency to remove the statistical noise. it will weight lower frequency components far more than higher frequency components and not provide an accurate estimate of the noise.

Shawn

Thank you for your support and quick response as always

"Your curve labeled "noise sim" does not appear to be the actual simulation data. It would be be best to superimpose the actual small-signal noise simulation over your transient noise PSD results."

Its actual simulation data:

I defined a noise source and ran noise simulation:

"The difference between the yellow and blue data at frequencies over 7 or 8 GHz is due to your choice of a 10 GHz noisefmax."

If I want to implement this on PLL actually I need up to 100MHz so 7-8GHz does not matter much.

"very few frequency points available for the low frequency range of the curve and the statistical error."

My BWres is around 1k so at 100k I have 100 freq points isnt that enough ?

"There is an option to run multiple transient noise simulations within the Transient Noise GUI - or you can simply repeat them with different seeds."

I did this before. Yes, I can run at least 3 simulation and take average PSD (My next plan)

"I do not recommend using a moving average function over frequency to remove the statistical noise. it will weight lower frequency components far more than higher frequency components and not provide an accurate estimate of the noise."

If I dont take moving average how am I supposed to see the exact PSD number ?

This is with 3 tran-noise simulations and taking average 

Fnoise - max is 5GHz here

Dear asrf,

I think my response was not sufficiently clear and I apologize for not being more precise!

asrf said:

Its actual simulation data:

I defined a noise source and ran noise simulation:

My apologies! I thought you were simulating the small-signal noise of your diode connected transistor as you noted in your initial Forum post:

asrf said:

I started with transient noise simulation of diode connected transistor voltage (Vn or Vnoise)

I now understand  you are now simulating a component with a user supplied noise function.

asrf said:

My BWres is around 1k so at 100k I have 100 freq points isnt that enough ?

I should have been more clear. I was referring to the frequencies between 1 kHz and 10 kHz where there are only ten points.

asrf said:

Yes, I can run at least 3 simulation and take average PSD (My next plan)

Great! I would consider running more than 3 if that is possible.

asrf said:

If I dont take moving average how am I supposed to see the exact PSD number ?

As you noted above, you take the average of the PSD results (in linear power domain) at a given frequency. Actual spectrum and phase noise analyzers take multiple measurements and average the results to reduce the variance of the measurement (for example, the phase noise analyzer E5052A). 

Taking a moving average applies a first-order lowpass filter over a range of frequencies and really does not have a theoretical basis for its use in this application.

Finally, with respect to our statistical discussion and your final figure in this response, I noted you elected to choose two maximum values (shown as +8 dB and +10 dB) suggesting the PSD result is far in excess of your expected response. However, you could just as well choose the two minimum values suggesting the response was far below your expected response. This is why the use of multiple transient noise analyses is recommended to reduce the statistical noise to a level where the the average provides a reasonable estimate of performance.

There are other ways to attack this issue that avoid the need to perform a lot of transient noise analyses to estimate the average noise response, but I think their discussion is a bit too off topic.

Shawn

Dear asrf,

My response was just flagged as spam again...hopefully it will be allowed to post.

Shawn

Dear asrf.

asrf said:

This is with 3 tran-noise simulations and taking average 

Are you averaging the linear data and not the logarithmic data?

Shawn

Thank you for your explanations:

yes in linear domain

10*log10((psd(leafValue( vtime('tran "/VNOISE") "FNOISE_MAX" 5e+09 "Iteration" 1 )  0.0 1.342m 67108864 ?windowName "Rectangular" ?windowSize 67108864)+psd(leafValue( vtime('tran "/VNOISE") "FNOISE_MAX" 5e+09 "Iteration" 2 )  0.0 1.342m 67108864 ?windowName "Rectangular" ?windowSize 67108864)+psd(leafValue( vtime('tran "/VNOISE") "FNOISE_MAX" 5e+09 "Iteration" 3 )  0.0 1.342m 67108864 ?windowName "Rectangular" ?windowSize 67108864))/3)

What if it is because my ResBw is a weird number ?  745.1 ?

This is out of control though we cannot make it a round number unless NFFT is not equal to 2^N

Dear asrf,

I studied your expressions and that is exactly the type of averaging I was suggesting - great!

asrf said:

What if it is because my ResBw is a weird number ?  745.1 ?

The only time the frequency bin width is considered important in a DFT/FFT/PSD analysis is if you are applying discrete tones at some frequency and are interesting in preventing leakage of the spectral components of the tone into adjacent frequency bins. In that case, the sampling rate relative to the frequency of the tone of interest and size of the DFT/FFT/PSD can be chosen to prevent spectral leakage using a conventional rectangular window. In your case, your noise is a wideband signal and one cannot choose a sample rate and DFT/FFT/PSD size to accommodate all the frequencies in your signal.

What I might suggest is you reduce your window size. At present, my understanding of your choice of window size is the length of your DFT (2^26). This will provide a maximum frequency resolution, but also maximum statistical error. If you reduce this value, multiple DFT are performed which will reduce the statistical noise.

Shawn