VerilogA for staircase voltage generator issue

This post shows a way to do this with a clocked source to trigger the transitions:  staircase function 

You could do it with @timer instead of a clocked source - it certainly would not be done with a for loop the way you've done it - using @cross to detect time crossings is not a good idea and you are creating a lot of cross events for every iteration of the loop (I know it's a genvar). It would make more sense to do something like (I only did very limited testing):

//
`include "constants.vams"
`include "disciplines.vams"

module staircase_voltage_generator(A, B);

inout A, B;
electrical A, B;

parameter real t_start = 100n;
parameter real stair_step_time = 10u;
parameter real stair_step_amplitude = 6m;
parameter real vo_begin = -60m;
parameter integer steps_number = 100;

parameter real td = 10p from [0:inf);
parameter real tr = 10p from (0:inf);
parameter real tf = 10p from (0:inf);

real vout;
integer i;

analog begin

  @ ( initial_step ) begin
   vout=vo_begin;
   i=0;
  end

  @(timer(t_start,stair_step_time)) begin
    if(i<steps_number) begin
      i++;
      vout=vout+stair_step_amplitude;
    end
  end

  V(A,B)<+transition(vout, td, tr, tf);

end

endmodule

Thank you for your reply, the code seems to be working fine.

Just for sake of understanding, what is wrong with the for loop?

There are n_steps loop iterations, each containing one cross function getting triggered once, timer function will get triggered n_steps times as well, is this correct? Where does the overhead lie?

And moreover, a part from the efficiency point of view, why is the for loop just not working? (or actually working only for the first step) Is it not correct to assume that @ cross( $abstime - t_start+i*stair_step_time, +1) would get triggered as tran sim time passes? If not, why? cross function should be able to evaluate any expression, is $abstime not an expression maybe?

Dear NewScreenName.

NewScreenName said:

Just for sake of understanding, what is wrong with the for loop?

I am not a veriloga expert, but when I looked at your source code, it seems that your for loop will run a single time after your begin statement. There is nothing limiting the advancement of your for loop counting integer i at a given time. Hence, it will simply complete the for loop after the begin statement and not trigger at each staircase transition time as you desire.

In Andrew's code, the timer serves to trigger a stairstep event at each desired time.

Shawn

The issue is not the loop (which is a genvar loop, so is expanded at "compilation time", so is equivalent to unrolling the loop and having lots of @ cross statements, one for each expanded time. The issue is that the argument is not an "analog signal" - and so that means (I believe) that the timestep control in the simulator can't iterate to resolve the crossing point accurately because it's not a function for which the derivative can be taken. The Verilog-AMS Language Reference Manual (LRM) is a little vague on this, but it does say: