Observing PLL Phase Noise with hbnoise

Dear illaoi,

illaoi said:

Consider an integer-N type-2 PLL with reference of 50 MHz and output frequency of 2400 MHz (N=48) with no behavioral model for any of the blocks (VCO, PFD, CP, Divider,...), all designed with PDK.

and

illaoi said:

I have tried both of them but in all cases, the simulation never converged (of course, I mean hb, or pss, when no oscillator has been selected), thus can anyone comment on if I took any steps wrong or any better way that I can do to obtain phase noise?

The fact that the PSS portion of your simulation sequence does not converge is not surprising illaoi for several reasons.

1. Even if your simulation converged, the divider ratio of 50 will stress the simulator and your computing resources (i.e., memory) as described in the Troubleshooting article at URL:

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000056dyEAA&pageName=ArticleContent

or by typing "spectre -h rfmemory".

2. As your PLL approaches its steady-state, the input and output frequencies are not identical. This alone prevents pss convergence as it requires that all frequencies in the steady-state are synchronous. If you try to include a long tstab interval to  allow the input and output frequency to be closer in frequency, you might as well consider running a transient simulation to examine steady-state performance in lieu of waiting the same time and only then start a pss analysis.

3. For these reasons, my understanding based on reference [1], is Cadence does not recommend using a pss/pnoise simulation to estimate PLL performance. In lieu of this, the use of a conventional transient or transient noise simulation is proposed.

From my experiences, we relied on transient analyses to evaluated PLL parameters such as settling, stability, phase offsets, reference spurs and other parametric. Phase noise of the PLL output was evaluated using a combination of behavioral models, pss/pnoise results for the VCO, and knowledge of the large signal PLL transfer functions.

I hope this provides some information to help you.

Shawn 

[1] https://community.cadence.com/cadence_technology_forums/f/rf-design/49390/pss-pnoise-simulation-for-vco-and-pll

Shawn,

Thanks for the reply, though let me clarify why this "In lieu of this, the use of a conventional transient or transient noise simulation is proposed." will not be practical.

Needless to say, transient is not goanna cut it since there is no noise from noisy components, therefore it must be tran noise for phase noise estimation. 

Consider 10 GHz oscillator that we are interested in seeing 10 MHz offset phase noise, that means, at least I need, 1/10M, 100ns of cycles, which would be 100ns/100ps, which is thousand cycles.

That would take a very long time for the whole PLL simulation. Also, do you recommend using PhaseNoise function as I mentioned?

Dear illaoi,

illaoi said:

Needless to say, transient is not goanna cut it since there is no noise from noisy components, therefore it must be tran noise for phase noise estimation. 

While you are absolutely correct that a conventional transient analysis will not provide an estimate of the phase noise of the output clock, there is merit in its use prior to performing a transient noise simulation. Why do I suggest this?

1. If you are planning to perform a transient noise analysis to estimate output phase noise, it is necessary to assure your simulator settings and simulation time are sufficient to provide an accurate model of the steady-state behavior of the phase-locked loop. Since a conventional transient simulation will require less computing resources than a transient noise simulation, verifying the simulator settings and settling behavior of the phase-locked loop with a conventional transient simulation is more efficient. With respect to this item, please also note my comment in response to your second comment below.

2. You may want to use the state variables from the end of your conventional transient simulation as initial conditions or nodesets for your transient noise simulation to expedite its settling time. As you know, with a high gain VCO (i.e., Kvco ~ GHz/V), knowledge of the nearly converged VCO control voltage can expedite settling to a particular frequency.

illaoi said:

Consider 10 GHz oscillator that we are interested in seeing 10 MHz offset phase noise, that means, at least I need, 1/10M, 100ns of cycles, which would be 100ns/100ps, which is thousand cycles.

That would take a very long time for the whole PLL simulation.

I totally understand your concern illaoi and have faced this same quandary! I also hesitate to add, but feel I should, that the situation you attempt to quantify is much worse.

As I mentioned in item (1), in order for a transient noise simulation to provide accurate results, the portion of the simulation you analyze for phase noise must represent near steady-state behavior. In the example you provided, you note: "that means, at least I need, 1/10M, 100ns of cycles, which would be 100ns/100ps, which is thousand cycles. That would take a very long time for the whole PLL simulation.". In reality, if you are simulating with real components, your integration time must be on the order of the minimum time feature or less. For example, your charge-pump (I assume yo meant your PLL is actually third-order) will produce pulses that are far far less than the period of the VCO. In addition, the change in VCO frequency per cycle will be far less than its period. I have worked with cases where the charge-pump offsets are only correctly estimated when the integration time step is on the order of ps for VCO in the 10 - 30 GHz range. These simulations take days and weeks to perform as they approach steady-state behavior. As I am sure you also know, an improper estimate of the charge-pump phase offset due to simulator accuracy settings will lead to an incorrect estimate of phase-locked loop sub-harmonics and hence an incorrect phase noise estimate.

So, in summary, yes, I fully acknowledge your comments with respect to simulating a phase-locked loop with real components (i.e., without behavioral views). This fact served as the motivation for my alternate suggestions. They are more time efficient and have proven themselves accurate in my experiences.

illaoi said:

Also, do you recommend using PhaseNoise function as I mentioned?

The phaseNoise() function is for use with a pss/pnoise based analysis and can be used following a converged pss/pnoise analysis. From the ViVA or ocean reference manuals, its input datasets are one of the following:

Signal dataset—Select the signal data set from the drop-down list. Available options: pss_fd, hb_fd, hb_mt_fi, and qpss_fi

For a transient noise simulation, phase noise is computed from the PSD. It can be obtained from the transient noise GUI (see Figure 4) , but I must warn you, a substantial amount of knowledge or experience with its arguments and simulator settings is necessary to produce a valid estimate of phase noise. it does produce valid results - but knowledge of the simulator and PSD/phase noise parameters is very important to assure the accuracy of the estimate. I am happy to help out if that is a path you decide to try.

I am sure my responses will put a frown on your face illaoi, but I must be honest in responding! Sorry!

Shawn

ShawnLogan said:

3. For these reasons, my understanding based on reference [1], is Cadence does not recommend using a pss/pnoise simulation to estimate PLL performance. In lieu of this, the use of a conventional transient or transient noise simulation is proposed.

OK, looking at that other post (your reference 1), the "no longer recommended" flow is the old PLL noise-aware flow which used a model-based approach for characterising blocks in the PLL - and this flow has been removed from the software. Tawna's additional recommendations about using transient noise are mainly pragmatic - because it's hard to get a PLL to converge. However, I have had customers with high divide ratio PLLs converge with PSS and get reasonably pnoise results - it is possible. 

Andrew

Dear Andrew,

Andrew Beckett said:

However, I have had customers with high divide ratio PLLs converge with PSS and get reasonably pnoise results - it is possible. 

Thank you for adding your experience with customers!

I don't doubt it is possible - but my guess is it was not a trivial process to both get convergence and then validate the results are reasonable.

In my personal experiences with large signal transistor based PLL simulations where I am studying parameters such as steady-state phase offsets and various loop parameters (dividers, Kvco, component variation, etc.), I've found it more time efficient to perform conventional transient simulations. Not only does this provide insight into the steady-state performance, but it also validates loop dynamics. For phase noise simulations, I never resorted to pss/pnoise simulations for phase noise. Using large signal pss/pnoise simulations for loop components combined with some post-processing always provided excellent phase noise correlation with measured data.

Please note, however, that I am only providing my personal experiences and do not even pretend to provide recommendations for everyone!

Shawn

I have extensively used PSS to analyse integer-N PLLs. Besides phase noise and jitter based on PNOISE, this approach is very useful to assess loop gain through PSTB and supply sensitivity with PAC/PXF. Whether transient noise or PNOISE is more efficient depends on the circumstances; if phase noise at very low offset frequencies are of interest, transient noise will quickly become unfeasible to run.

Based on my experience, I can give the following hints how to run such simulations:

• Use PSS, not HB. HB has a strong tendency to stall in convergence on such large circuits.
• The initial transient has to be long enough such that the PLL has locked well. Using auxiliary structures to pre-charge the VCO tuning voltage will speed up lock time.
• 'maxperiods' usually needs to be increased to say 100.
• 'reltol' might need to be pretty tight (several orders of magnitude tighter than the defaults). As far as I understand, the issue is that the VCO frequency easily drifts with relaxed tolerances, which makes PSS convergence more difficult. Unfortunately, PSS does not support individual 'reltol' settings for sub-circuits (regular transient does).
• Use the 'sampleratio' parameter with sampled PNOISE to enable wideband phase noise/jitter analysis up to half the output clock frequency.
• PSTB seems to have pronounced numerical issues at low analysis frequencies; so don't be scared if the loop gain suddenly drops again towards lower frequencies. Near the unity gain frequency, the results seem reliably, so stability can be assessed.