Observing PLL Phase Noise with hbnoise

Dear illaoi,

illaoi said:

Consider an integer-N type-2 PLL with reference of 50 MHz and output frequency of 2400 MHz (N=48) with no behavioral model for any of the blocks (VCO, PFD, CP, Divider,...), all designed with PDK.

and

illaoi said:

I have tried both of them but in all cases, the simulation never converged (of course, I mean hb, or pss, when no oscillator has been selected), thus can anyone comment on if I took any steps wrong or any better way that I can do to obtain phase noise?

The fact that the PSS portion of your simulation sequence does not converge is not surprising illaoi for several reasons.

1. Even if your simulation converged, the divider ratio of 50 will stress the simulator and your computing resources (i.e., memory) as described in the Troubleshooting article at URL:

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000056dyEAA&pageName=ArticleContent

or by typing "spectre -h rfmemory".

2. As your PLL approaches its steady-state, the input and output frequencies are not identical. This alone prevents pss convergence as it requires that all frequencies in the steady-state are synchronous. If you try to include a long tstab interval to  allow the input and output frequency to be closer in frequency, you might as well consider running a transient simulation to examine steady-state performance in lieu of waiting the same time and only then start a pss analysis.

3. For these reasons, my understanding based on reference [1], is Cadence does not recommend using a pss/pnoise simulation to estimate PLL performance. In lieu of this, the use of a conventional transient or transient noise simulation is proposed.

From my experiences, we relied on transient analyses to evaluated PLL parameters such as settling, stability, phase offsets, reference spurs and other parametric. Phase noise of the PLL output was evaluated using a combination of behavioral models, pss/pnoise results for the VCO, and knowledge of the large signal PLL transfer functions.

I hope this provides some information to help you.

Shawn 

[1] https://community.cadence.com/cadence_technology_forums/f/rf-design/49390/pss-pnoise-simulation-for-vco-and-pll

ShawnLogan said:

3. For these reasons, my understanding based on reference [1], is Cadence does not recommend using a pss/pnoise simulation to estimate PLL performance. In lieu of this, the use of a conventional transient or transient noise simulation is proposed.

OK, looking at that other post (your reference 1), the "no longer recommended" flow is the old PLL noise-aware flow which used a model-based approach for characterising blocks in the PLL - and this flow has been removed from the software. Tawna's additional recommendations about using transient noise are mainly pragmatic - because it's hard to get a PLL to converge. However, I have had customers with high divide ratio PLLs converge with PSS and get reasonably pnoise results - it is possible. 

Andrew

Dear Andrew,

Andrew Beckett said:

However, I have had customers with high divide ratio PLLs converge with PSS and get reasonably pnoise results - it is possible. 

Thank you for adding your experience with customers!

I don't doubt it is possible - but my guess is it was not a trivial process to both get convergence and then validate the results are reasonable.

In my personal experiences with large signal transistor based PLL simulations where I am studying parameters such as steady-state phase offsets and various loop parameters (dividers, Kvco, component variation, etc.), I've found it more time efficient to perform conventional transient simulations. Not only does this provide insight into the steady-state performance, but it also validates loop dynamics. For phase noise simulations, I never resorted to pss/pnoise simulations for phase noise. Using large signal pss/pnoise simulations for loop components combined with some post-processing always provided excellent phase noise correlation with measured data.

Please note, however, that I am only providing my personal experiences and do not even pretend to provide recommendations for everyone!

Shawn

Dear Andrew,

Andrew Beckett said:

However, I have had customers with high divide ratio PLLs converge with PSS and get reasonably pnoise results - it is possible. 

Thank you for adding your experience with customers!

I don't doubt it is possible - but my guess is it was not a trivial process to both get convergence and then validate the results are reasonable.

In my personal experiences with large signal transistor based PLL simulations where I am studying parameters such as steady-state phase offsets and various loop parameters (dividers, Kvco, component variation, etc.), I've found it more time efficient to perform conventional transient simulations. Not only does this provide insight into the steady-state performance, but it also validates loop dynamics. For phase noise simulations, I never resorted to pss/pnoise simulations for phase noise. Using large signal pss/pnoise simulations for loop components combined with some post-processing always provided excellent phase noise correlation with measured data.

Please note, however, that I am only providing my personal experiences and do not even pretend to provide recommendations for everyone!

Shawn

I have extensively used PSS to analyse integer-N PLLs. Besides phase noise and jitter based on PNOISE, this approach is very useful to assess loop gain through PSTB and supply sensitivity with PAC/PXF. Whether transient noise or PNOISE is more efficient depends on the circumstances; if phase noise at very low offset frequencies are of interest, transient noise will quickly become unfeasible to run.

Based on my experience, I can give the following hints how to run such simulations:

• Use PSS, not HB. HB has a strong tendency to stall in convergence on such large circuits.
• The initial transient has to be long enough such that the PLL has locked well. Using auxiliary structures to pre-charge the VCO tuning voltage will speed up lock time.
• 'maxperiods' usually needs to be increased to say 100.
• 'reltol' might need to be pretty tight (several orders of magnitude tighter than the defaults). As far as I understand, the issue is that the VCO frequency easily drifts with relaxed tolerances, which makes PSS convergence more difficult. Unfortunately, PSS does not support individual 'reltol' settings for sub-circuits (regular transient does).
• Use the 'sampleratio' parameter with sampled PNOISE to enable wideband phase noise/jitter analysis up to half the output clock frequency.
• PSTB seems to have pronounced numerical issues at low analysis frequencies; so don't be scared if the loop gain suddenly drops again towards lower frequencies. Near the unity gain frequency, the results seem reliably, so stability can be assessed.