PLL noise verification problem (Cadence PLL RAK)

Dear KGSpll,

KGSpll said:

After Transistor-level PFD_CP Noise simulation, we can get the output phase noise plot,

but the TR-model noise result is -176 dBA/Hz

there's mismatch between pll_phase_domain model and TR_level noise plot.

So I think RAK model change output noise noise to input referred noise

However, the calculation result is not same too.

So, this value: -192.9
Where it came from ?? is there something I missed?

I must admit I may not be understanding your question correctly and, to be honest, am having difficulty viewing your posted images as the resolution is poor. However, let me pose a thought or two in case any of them are of use to you.

I reviewed the PLL RAK to which you referred which reviews a number of simulations. The note includes examples of  both large signal and small signal simulations to study model various loop components or subsets of loop components and ends with a functional simulation of the entire fractional N phase-locked loop.

1. With respect to the circled value of "-192.9" shown in the image of the instance Ipfd_cp of cell VNoiseFlickerWhite for parameter "flickerPSDat1Hz", this value is from a transistor level PSS/pnoise simulation of the PFD and charge-pump subcircuits. Similarly, the value of parameter "whitePSD" of 10**(-235/10) is also from the same PSS/pnoise simulation of the PFD and charge-pump simulation. Basically, these two values from the transistor level PSS/pnoise simulation of the two components are used in a verilog-A based noise source to model the noise of the two.

2. If you examine the example PSS/pnoise simulation of the PFD and charge-pump subcircuits provided in the RAK, you will note that the extrapolated 1 Hz 1/f noise value (see Figure 1 below) appears much greater than the specified value of -192.9 dB A/root Hz (dB) and the flat noise region appears to be less than the -229 A/root Hz (dB) values shown in the unlabeled phase noise plot on page 55 of the RAK.

Why do the two values differ from those shown in your pasted images? They differ because the values shown in the phase noise plot on page 55 represent a PSS/pnoise simulation where the overlap between the reference and feedback clocks to the PFD input is set to the variable "dt" and "dt" was set to a value of 10 ps. ("dt" represents the static phase offset of the phase-locked loop).  The greater the value of "dt", the greater the phase contribution of the PFD/CP to the overall loop phase noise. As noted in the example, the variable "dt" is set to the simulated value of the static phase offset. The value of 10 ps was only selected for the example on page 55. Most likely, the static phase offset is much less than 10 ps and hence the phase noise contribution of the PFD/CP blocks will be less than that shown on page 55. The 1 Hz 1/f value of -192.9 A/root Hz (dB) value corresponds to the result of a PSS/pnoise simulation where "dt" was set to the expected value for the loop static phase offset and much less than 10 ps.

The text of the RAK on pages 50 and 51 indicates:

"Note that the two periodic noise sources are offset by dt - a design variable that you will set to 10ps later in ADE Explorer. You can experiment with this variable to see how the resulting noise changes (larger dt, higher noise). Ideally, you will put a value closer to the situation when the PLL locks."

Shawn

Figure 1

Extrapolate Phase Noise Characteristic of PFD/CP Transistor Level Simulation to Highlight 1 Hz 1/f noise value and Thermal Noise Floor with Simulation Parameter "dt" (static phase offset) set to 10 ps

(from page 55 of RAK "PLL Verification", Product Version IC 6.1.8, MMSIM 21.1, XCELIUM 21.09 May, 2022)

Thank you very much for your reply.

Please confirm that my understanding is correct.

In summary, after measuring the output phase noise value at the transistor-level,

a schematic called pll_phase_domain is made with a verilog-A model to analyze the noise shaping characteristics of each block or the noise characteristics of the entire PLL model.

From your answer, my understanding is that the two noise inputs are different because in most cases they appear less than dt=10ps.

If I interpret it in my own way, I think the setting value of dt=10ps is the worst-case situation.

However, the noise input for pll_phase_domain ( -192.9[dBA/ root Hz] ) is confusing the user.
This is because, as mentioned earlier,

it is different from the actual measured value ( -172[dBA/ root Hz] ) at the transistor-level set as dt=10ps.

I may not have been able to figure this out due to my lack of understanding,

but at least RAK should have made it clear why the two values differ in the PDF file:

( As ShawnLogan said, the actual static phase offset is less than 10 ps, so the noise input value is different. )

- Question about VCO Noise model

Also, this is a question about the input referred noise mentioned in the PFD_CP block.

(According to the results concluded above, the noise value of PFD_CP seems to be input as the output noise value.)

Let me tell you why I interpreted it in the <Input referred noise> way in the first place.

This is because in the VCO noise model, the input noise is multiplied by Laplace's formula in the VCVS model.

The value 2*6.28*(50e6/s) is multiplied, where 6.28 is 2pi, and 50e6/s can be interpreted as a formula that reflects the VCO's Kvco, but I'm not sure what the value of 2 means.

In the RAK file :

VCO2G5 instance represents the cascaded chain of the VCO, Buffer, and DIV2 Divider blocks

It is specified in RAK that the model VCO2G5 is a model expressed as VCO + Buffer + DIV2, but if the input referred noise is simply converted to the output noise value by multiplying the gain, the gain value of DIV2 (frequency divider) is 1/2, It should be expressed as (1/2)*6.28*50e6/s, not 2*6.28*50e6/s.

And, unfortunately, the RAK file only provides noise simulation for the VCO core, not VCO2G5 (VCO+Buffer+Divider).

(Please let me know if there is anything I couldn't find.)

The noise result of the VCO core is (Relative Freqeuncy : 1Hz) , +50 dBV/Hz, +55 dBc/Hz.

Another question here is that the value of +55 dBc/Hz is the result that noise is greater than the input signal. (???)

I would like to ask if this is possible with common sense.

There are three main questions.
1. Is it correct to convert the VCO noise value into Input Referred Noise?
1. VCO noise model: Meaning of 2* in 2*6.28*50e6/s
2. VCO Output Noise: Is +55dBc/Hz value possible at 1Hz?

: PLL_phase_domain, VCO Noise model

: PLL_phase_domain, maestro , Design Variable ( Please see Kvco value, It's not equal to 50e6.)

Transistor-level VCO Noise simulation result

- Result of hand calculation (not matched)

Dear KGSpll,

KGSpll said:

Please confirm that my understanding is correct.

---

In summary, after measuring the output phase noise value at the transistor-level,

a schematic called pll_phase_domain is made with a verilog-A model to analyze the noise shaping characteristics of each block or the noise characteristics of the entire PLL model.

I think there may be some confusion from this question. A verilog-A model does not necessarily have a schematic view. It may, but as a minimum the cell has a symbol view and a behavioral view (veriloga). The schematic pll_phase_domain_sim has several cells whose views are specified as behavioral views (veriloga). The values for the variables for the verilog-A based noise models for each loop components are obtained from individual transistor level simulations of the relevant subcircuits.

KGSpll said:

From your answer, my understanding is that the two noise inputs are different because in most cases they appear less than dt=10ps.

If I interpret it in my own way, I think the setting value of dt=10ps is the worst-case situation.

Yes. The value of parameter "dt"  chosen for the verilog-A model of the phase detector/charge-pump behavioral block is based on the simulated value of static phase offset and not the example value of 10 ps that produced the phase noise plot shown in the RAK. The RAK indicates the PFD input frequencies are 20 MHz. Hence a 10 ps static phase offset represents 0.20 mUI, but is 0.05 UI of the 5 GHz VCO. This value appears to be rather large and will result in significant deterministic jitter. 

KGSpll said:

However, the noise input for pll_phase_domain ( -192.9[dBA/ root Hz] ) is confusing the user.
This is because, as mentioned earlier,

it is different from the actual measured value ( -172[dBA/ root Hz] ) at the transistor-level set as dt=10ps.

---

I may not have been able to figure this out due to my lack of understanding,

but at least RAK should have made it clear why the two values differ in the PDF file:

( As ShawnLogan said, the actual static phase offset is less than 10 ps, so the noise input value is different. )

Your last statement is correct from my understanding - the phase noise plot of the stand-alone pfd/charge-pump shown in the RAK represents the "example" value of "dt" = 10 ps. The value of "dt" in the noise model parameter of the pfd/charge-pump noise model in the PLL noise simulation does not use "dt" = 10 ps, but uses a value representative of the expected static phase offset - which is less than 10 ps . I cannot comment on the RAK as I do not work for Cadence. You can certainly file a case with them to request the documentation be modified more to your liking.

Shawn

Dear KGSpll,

KGSpll said:

- Question about VCO Noise model

Also, this is a question about the input referred noise mentioned in the PFD_CP block.

(According to the results concluded above, the noise value of PFD_CP seems to be input as the output noise value.)

This is not correct. The simulation performed in the example provides the phase noise at the output of the combined pfd/charge-pump block.

Please study the pnoise GUI on page 54 of the RAK where it clearly indicates the output is Vcp_out. 

KGSpll said:

This is because in the VCO noise model, the input noise is multiplied by Laplace's formula in the VCVS model.

The value 2*6.28*(50e6/s) is multiplied, where 6.28 is 2pi, and 50e6/s can be interpreted as a formula that reflects the VCO's Kvco, but I'm not sure what the value of 2 means.

I do not have visibility into the verilog-A view of the noise model, but in the ADE design variable window shown below the 2.5 GHz Kvco value in MHz/V is 48 MHz/V - which is about 1/2 the value of 90 MHz/V for the standalone 5 GHz VCO simulation.

KGSpll said:

Another question here is that the value of +55 dBc/Hz is the result that noise is greater than the input signal. (???)

I would like to ask if this is possible with common sense.

The vertical axis of the plot you are referring to is not in dBc/Hz - it is is in dBV/Hz and hence your comment is not applicable. Please double-check the units that I have circled from your plot.

Shawn

Again, I am very grateful for your answer. Thank you.

Since you answered my question, I've been thinking about it.

I will divide it into four areas.

1. dt=10ps 

2.Input Referred Noise

3. Kvco value

4. dBc Plot

1. dt=10ps 

ShawnLogan said:

The RAK indicates the PFD input frequencies are 20 MHz. Hence a 10 ps static phase offset represents 0.20 mUI, but is 0.05 UI of the 5 GHz VCO. This value appears to be rather large and will result in significant deterministic jitter. 

Since the period of 5GHz is 0.2ns, we said that the value of dt=10ps has a ratio of 0.05 to 0.2ns.
This produces a large jitter value for a significant proportion.

But in the end, the VCO output is divided at DIV and feedback to the PFD,

so I don't agree with the explanation you gave as an example. I don't know why the ratio of 10ps on a 5GHz VCO matters.

The meaning of dt in the current PFD_CP block is a situation where the values of the two signals (REF, DIV) are different.

(More precisely, the Reference signal is generated first, followed by the Divider signal to generate the Up signal)
It means that noise occurs when PFD_CP operates as much as dt=10ps.

And in the first answer, it was said that the value of 10ps corresponds to a larger static phase offset value in normal circumstances,

so a larger value (-172~) than expected noise value (-192~) comes out.

But in your example: in a Reference of 20MHz, dt=10ps is a ratio of 0.2m.

Is a value with a ratio of 0.2m (0.2*10^-3) in the entire period really a large value?

So, is the ratio of 0.2m a large static phase offset? -> A question arises.

-The question I asked at the beginning:

Why is the noise value measured at pll_phase_domain different from the noise value measured at TR-Level?
I don't know if the answer you gave at the beginning of this question (dt=10ps is quite large under normal circumstances) is correct.

2. Input Referred Noise

Noise modeling of PFD_CP and VCO in pll_phase_domain is different.
In the form of an Adder to the output terminal of each Block,

2-1. For PFD_CP, the value measured at TR-Level is directly entered. (VCVS model, *1 )

2-2. VCO is multiplied by Laplace's formula (VCVS model, 2*6.28*(50e6/s)).

For this reason, PFD_CP means that the Output Phase Noise (measured) value is directly input.
Isn't the VCO Ouput Phase Noise converted to Input Referred Noise? This is what I asked you.

3. Kvco value

ShawnLogan said:

2.5 GHz Kvco value in MHz/V is 48 MHz/V - which is about 1/2 the value of 90 MHz/V for the standalone 5 GHz VCO simulation.

I'm not sure why the Kvco at 2.5GHz is 48MHz/V (approximately 45).
The averaged Kvco of the 5GHz VCO is 90MHz/V. Does that mean it is divided by 2 to reflect DIV2?
I understood it to mean that input referred noise was multiplied by VCO gain (Kvco/s) * DIV gain (1/2) and converted to Output Phase noise.

Why does [2*6.28*(50e6/s) ] 2* still exist,

and the Kvco value is 50e6, which does not match the value of 45e6 suggested by maestro?

4. dBc Plot

Sorry for the confusion. Attach the dBc Plot again.
However, the essence of the question is that

if the dBc value is positive at Relative Freq.=1Hz, the noise signal is greater than the VCO signal.
I was asking if this is possible with common sense.

Dear KGSpll,

KGSpll said:

Since the period of 5GHz is 0.2ns, we said that the value of dt=10ps has a ratio of 0.05 to 0.2ns.
This produces a large jitter value for a significant proportion.

But in the end, the VCO output is divided at DIV and feedback to the PFD,

so I don't agree with the explanation you gave as an example. I don't know why the ratio of 10ps on a 5GHz VCO matters.

In most all frequency synthesizers, the output clock of interest is the high frequency clock - not the low frequency reference clock. The high frequency clock is divided down to the low frequency clock rate in order that the PFD design is manageable. In essence, it is very difficult to design a 5 GHz PFD, but a 20 MHz PFD is much easier to design. Hence, the static phase offset, "dt", is most relevant with respect to the high frequency clock - in this case 5 GHz - and not the low frequency reference clock of 20 MHz.

KGSpll said:

The question I asked at the beginning:

Why is the noise value measured at pll_phase_domain different from the noise value measured at TR-Level?
I don't know if the answer you gave at the beginning of this question (dt=10ps is quite large under normal circumstances) is correct.

I tied to answer your first question several times now. I guess my answers are not clear. The 10 ps value that was used in the example PSS/pnoise simulation results is NOT the value used in PSS/pnoise result that feeds the verilog-A model. I don't know how else to more clearly state this. I just answered your second point.

KGSpll said:

2-2. VCO is multiplied by Laplace's formula (VCVS model, 2*6.28*(50e6/s)).

The screen shot you are displaying does not suggest this is an operation to me. The symbol terminal which is what that looks like), unless the CDF is displayed on the symbol, is not representative of the subcircuit operation. I do not have visibility into the schematic and hence can not comment. I suggest you study the netlist  (input.scs file) for this simulation to see how the noise model is applied.

KGSpll said:

For this reason, PFD_CP means that the Output Phase Noise (measured) value is directly input.
Isn't the VCO Ouput Phase Noise converted to Input Referred Noise? This is what I asked you.

I answered this already. No. Nether the PFD/Cp noise measurement nor the VCO phase noise measurements are "input referred". Please study how they are individually performed and this should be clear.

KGSpll said:

Sorry for the confusion. Attach the dBc Plot again.
However, the essence of the question is that

if the dBc value is positive at Relative Freq.=1Hz, the noise signal is greater than the VCO signal.
I was asking if this is possible with common sense.

Please refer to Section 2.1 of the note at URL:

www.dropbox.com/s/5za1ilay6sqa06b/phase_noise_response_081422v1p0.pdf?dl=0

regarding the use of spectral density based measurements or simulation results to represent phase noise for values greater than about -20 dbc/Hz.

Please also note that is is possible for a phase noise component to exceed 1 unit interval. For example, components of phase noise in the wander region frequently exceed 1 UI.

Shawn