PLL noise verification problem (Cadence PLL RAK)

Dear KGSpll,

KGSpll said:

After Transistor-level PFD_CP Noise simulation, we can get the output phase noise plot,

but the TR-model noise result is -176 dBA/Hz

there's mismatch between pll_phase_domain model and TR_level noise plot.

So I think RAK model change output noise noise to input referred noise

However, the calculation result is not same too.

So, this value: -192.9
Where it came from ?? is there something I missed?

I must admit I may not be understanding your question correctly and, to be honest, am having difficulty viewing your posted images as the resolution is poor. However, let me pose a thought or two in case any of them are of use to you.

I reviewed the PLL RAK to which you referred which reviews a number of simulations. The note includes examples of  both large signal and small signal simulations to study model various loop components or subsets of loop components and ends with a functional simulation of the entire fractional N phase-locked loop.

1. With respect to the circled value of "-192.9" shown in the image of the instance Ipfd_cp of cell VNoiseFlickerWhite for parameter "flickerPSDat1Hz", this value is from a transistor level PSS/pnoise simulation of the PFD and charge-pump subcircuits. Similarly, the value of parameter "whitePSD" of 10**(-235/10) is also from the same PSS/pnoise simulation of the PFD and charge-pump simulation. Basically, these two values from the transistor level PSS/pnoise simulation of the two components are used in a verilog-A based noise source to model the noise of the two.

2. If you examine the example PSS/pnoise simulation of the PFD and charge-pump subcircuits provided in the RAK, you will note that the extrapolated 1 Hz 1/f noise value (see Figure 1 below) appears much greater than the specified value of -192.9 dB A/root Hz (dB) and the flat noise region appears to be less than the -229 A/root Hz (dB) values shown in the unlabeled phase noise plot on page 55 of the RAK.

Why do the two values differ from those shown in your pasted images? They differ because the values shown in the phase noise plot on page 55 represent a PSS/pnoise simulation where the overlap between the reference and feedback clocks to the PFD input is set to the variable "dt" and "dt" was set to a value of 10 ps. ("dt" represents the static phase offset of the phase-locked loop).  The greater the value of "dt", the greater the phase contribution of the PFD/CP to the overall loop phase noise. As noted in the example, the variable "dt" is set to the simulated value of the static phase offset. The value of 10 ps was only selected for the example on page 55. Most likely, the static phase offset is much less than 10 ps and hence the phase noise contribution of the PFD/CP blocks will be less than that shown on page 55. The 1 Hz 1/f value of -192.9 A/root Hz (dB) value corresponds to the result of a PSS/pnoise simulation where "dt" was set to the expected value for the loop static phase offset and much less than 10 ps.

The text of the RAK on pages 50 and 51 indicates:

"Note that the two periodic noise sources are offset by dt - a design variable that you will set to 10ps later in ADE Explorer. You can experiment with this variable to see how the resulting noise changes (larger dt, higher noise). Ideally, you will put a value closer to the situation when the PLL locks."

Shawn

Figure 1

Extrapolate Phase Noise Characteristic of PFD/CP Transistor Level Simulation to Highlight 1 Hz 1/f noise value and Thermal Noise Floor with Simulation Parameter "dt" (static phase offset) set to 10 ps

(from page 55 of RAK "PLL Verification", Product Version IC 6.1.8, MMSIM 21.1, XCELIUM 21.09 May, 2022)

- Question about VCO Noise model

Also, this is a question about the input referred noise mentioned in the PFD_CP block.

(According to the results concluded above, the noise value of PFD_CP seems to be input as the output noise value.)

Let me tell you why I interpreted it in the <Input referred noise> way in the first place.

This is because in the VCO noise model, the input noise is multiplied by Laplace's formula in the VCVS model.

The value 2*6.28*(50e6/s) is multiplied, where 6.28 is 2pi, and 50e6/s can be interpreted as a formula that reflects the VCO's Kvco, but I'm not sure what the value of 2 means.

In the RAK file :

VCO2G5 instance represents the cascaded chain of the VCO, Buffer, and DIV2 Divider blocks

It is specified in RAK that the model VCO2G5 is a model expressed as VCO + Buffer + DIV2, but if the input referred noise is simply converted to the output noise value by multiplying the gain, the gain value of DIV2 (frequency divider) is 1/2, It should be expressed as (1/2)*6.28*50e6/s, not 2*6.28*50e6/s.

And, unfortunately, the RAK file only provides noise simulation for the VCO core, not VCO2G5 (VCO+Buffer+Divider).

(Please let me know if there is anything I couldn't find.)

The noise result of the VCO core is (Relative Freqeuncy : 1Hz) , +50 dBV/Hz, +55 dBc/Hz.

Another question here is that the value of +55 dBc/Hz is the result that noise is greater than the input signal. (???)

I would like to ask if this is possible with common sense.

There are three main questions.
1. Is it correct to convert the VCO noise value into Input Referred Noise?
1. VCO noise model: Meaning of 2* in 2*6.28*50e6/s
2. VCO Output Noise: Is +55dBc/Hz value possible at 1Hz?

- Question about VCO Noise model

Also, this is a question about the input referred noise mentioned in the PFD_CP block.

(According to the results concluded above, the noise value of PFD_CP seems to be input as the output noise value.)

Let me tell you why I interpreted it in the <Input referred noise> way in the first place.

This is because in the VCO noise model, the input noise is multiplied by Laplace's formula in the VCVS model.

The value 2*6.28*(50e6/s) is multiplied, where 6.28 is 2pi, and 50e6/s can be interpreted as a formula that reflects the VCO's Kvco, but I'm not sure what the value of 2 means.

In the RAK file :

VCO2G5 instance represents the cascaded chain of the VCO, Buffer, and DIV2 Divider blocks

It is specified in RAK that the model VCO2G5 is a model expressed as VCO + Buffer + DIV2, but if the input referred noise is simply converted to the output noise value by multiplying the gain, the gain value of DIV2 (frequency divider) is 1/2, It should be expressed as (1/2)*6.28*50e6/s, not 2*6.28*50e6/s.

And, unfortunately, the RAK file only provides noise simulation for the VCO core, not VCO2G5 (VCO+Buffer+Divider).

(Please let me know if there is anything I couldn't find.)

The noise result of the VCO core is (Relative Freqeuncy : 1Hz) , +50 dBV/Hz, +55 dBc/Hz.

Another question here is that the value of +55 dBc/Hz is the result that noise is greater than the input signal. (???)

I would like to ask if this is possible with common sense.

There are three main questions.
1. Is it correct to convert the VCO noise value into Input Referred Noise?
1. VCO noise model: Meaning of 2* in 2*6.28*50e6/s
2. VCO Output Noise: Is +55dBc/Hz value possible at 1Hz?