transient temperature plot

Dea rsjwprcker,

sjwprcker said:

I would like to plot transient temperature in viva using ams sim environment. 

The experience with spectre is, a non-connected net with name "temp". Its waveform represents tran temperature. 

However, this solution doesn't work in ams environment. 

Is there any way similar working in ams environment then?

If you have any verilog-A based subcircuits in your netlist, or care to create a custom block, there are a couple of functions that can be used to both set and read the current temperature. Specifically, the $temperature function may be invoked to obtain the ambient temperature of a circuit in degrees Kelvin and $cds_set_temperature() can be called during simulation to change the global temperature (alternative to dynamic parameter simulation).

There is an old Forum post with an example and discussion with Andrew. The post also mentions a bug which I assume has been addressed.

community.cadence.com/.../verilog-a-model-and-temperature-in-ac-sim

I hope I understood your need and this helps!

Shawn

Shawn,

I don't think that's what sjwprcker is asking. I think they are asking about the trick of adding a dummy node in the schematic called temp which is not connected to anything as a means of having something in the schematic to ask to save - which generates a save statement "save temp". Then when using dynamic parameters (I assume they are using that too, although it would have been helpful to say) you can then plot the temperature versus time.

Strictly speaking the dummy node is just a means to generate the save statement, and the issue is that with AMS the nodes end up being scoped to the top level test bench and so (I assume) that it simply doesn't find the resulting signal afterwards.

The solution (which works for spectre too - you don't then need the unconnected temp node in the schematic) is to create a file called (say) savestuff.scs with the contents:

save temp

Then add this via Setup→Simulation Files→Definition Files.

Having done that, you would be able to access the temp signal from the results browser. Or by using VT("temp") .

By the way Shawn, the bug that I mentioned in the other post was indeed fixed, back in mid-2018.

Regards,

Andrew

Dear Andrew,

Andrew Beckett said:

I don't think that's what sjwprcker is asking. I think they are asking about the trick of adding a dummy node in the schematic called temp which is not connected to anything as a means of having something in the schematic to ask to save - which generates a save statement "save temp".

I did catch that, but since he indicated it did not work, I thought a verilog-A solution might be compatible with the schematic and might be a feasible solution. I did not know using the "save temp" statement in an AMS simulation would work if the use of the "dummy node" did not and hence did not suggest that.

Andrew Beckett said:

By the way Shawn, the bug that I mentioned in the other post was indeed fixed, back in mid-2018.

Great! Thank you for letting me know!

Shawn

Hi Andrew,

Your solution works perfectly. I think the verilogA model also works well. I prefer the signal saving solution. 

BR

Hi Andrew,

Your solution works perfectly. I think the verilogA model also works well. I prefer the signal saving solution. 

BR