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How to compare the before and after extraction values of resistance and capacitance?

Vishesh Gupta

Hi, 

I made a layout of a circuit which has a capacitance used in it. The capacitance used is a nmos capacitor. Is there any way I can compare the values of this capacitor before and after extraction (maybe a table that I can get)? I also want to know how the algorithm in the software has treated the capacitor? In other words, does the software breaks the capacitor in a pi network or star network, etc. in the extracted view.

Thanks and Regards,

Vishesh

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  • Dear Vishesh,

    Vishesh Gupta said:
    Is there any way I can compare the values of this capacitor before and after extraction (maybe a table that I can get)?

    A common method to compare the effective impedance of a schematic view and layout based view (extracted view) is to perform a large-signal or small-signal impedance simulation and print or plot the results. For a non-linear capacitor whose capacitance varies with DC bias, a large signal impedance simulation might be best as it will indicate the effective capacitance for the amplitude and bias values you apply in your simulation. For a fixed capacitor, a small-signal impedance simulation might be more appropriate.

    For your reference, I have provided a test bench and means of estimating the C-V characteristics of an arbitrary circuit at the post:

    community.cadence.com/.../capacitance-vs-bias-voltage-curve-for-ferroelectric-varactor

    I also included the expressions to compute the effective capacitance and real impedance of the device under test. Perhaps this will provide some insight into estimating the effective output capacitance of your device.

    Shawn

Reply

  • Dear Vishesh,

    Vishesh Gupta said:
    Is there any way I can compare the values of this capacitor before and after extraction (maybe a table that I can get)?

    A common method to compare the effective impedance of a schematic view and layout based view (extracted view) is to perform a large-signal or small-signal impedance simulation and print or plot the results. For a non-linear capacitor whose capacitance varies with DC bias, a large signal impedance simulation might be best as it will indicate the effective capacitance for the amplitude and bias values you apply in your simulation. For a fixed capacitor, a small-signal impedance simulation might be more appropriate.

    For your reference, I have provided a test bench and means of estimating the C-V characteristics of an arbitrary circuit at the post:

    community.cadence.com/.../capacitance-vs-bias-voltage-curve-for-ferroelectric-varactor

    I also included the expressions to compute the effective capacitance and real impedance of the device under test. Perhaps this will provide some insight into estimating the effective output capacitance of your device.

    Shawn

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