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Spectre warning: there are some nodes and instances from the netlist topology check.

ppptt

Hello everyone!

When I complete the layout of a cmos inverter and try to implement the post-simulation of it, there is a warning:

It reminds me that some instances (source and load) and nodes are dangling and removed during the simulation so that no waveform generates after the simulation, but the pre-simulation is normal.

This is my circuit:

I wonder what causes it and if there is a method to solve it.

Thanks in advance for any ideas on how to best overcome this problem!

Maioca

Parents

  • It sounds as if something is seriously wrong with the post-layout extraction - it suggests that the internals are not connected to the pins. What extraction tool are you using? What format are you extracting to - and have you checked the netlist to see if it all looks OK?

    Contacting customer support is probably the best option here.

    Andrew

Reply

  • It sounds as if something is seriously wrong with the post-layout extraction - it suggests that the internals are not connected to the pins. What extraction tool are you using? What format are you extracting to - and have you checked the netlist to see if it all looks OK?

    Contacting customer support is probably the best option here.

    Andrew

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