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LVS of a mixed signal design with a digital IP block?

kenc184

I have finished the design and layout of an analog/mixed signal chip. There is a digital IP block to be included.  I can DRC and LVS the entire design successfully if the digital block is removed from the layout and the schematic. 

The symbol for the IP block is empty, it just indicates the top level connectivity. There is a .subckt for the IP block. So far, I have been unsuccessful in getting the  netlister to include a subckt call (of the X111 a b c d e ipblock type) in the netlist. 

There is no schematic for the IP block, just the symbol.

I suppose I could ask the ?IP designer to auto generate a schematic from verilog - I think it has that capability?

But is there a simple way to get the symbol to generate the subcircuit call in the netlist and simply include the netlist as a spice file in LVS?

As an example, I created a very simple case with the IP block, a standard cell, and a custom cell, then created a netlist with CIW>File>export>CDL.  I have fiddled with stop views and switch views to no avail.

As you can see, there is no mention of x274.

  • RobMan

    Have you created the auCdl (stop) view for the netlister? If not copy the 'symbol' to the 'auCdl' view.

    Depending on how the symbol was created you might need to update the CDF. If necessary; Open the symbol and run the following SKILL.

        artGenerateHierSymbolCDF(geGetEditCellView())

  • kenc184
    in reply to RobMan

    Thanks RobMan, I'm not sure which one of your two suggestions worked, but I now have the .subckt "call" included in the netlist.

    I wish I had asked earlier!

  • kenc184
    in reply to RobMan

    The strange thing is: the verilog created  ip .subckt has a different pinorder than that which the analog netlister creates.  I found an old post where it was suggested to include auCdlCDFPinCntrl=t in a .simrc file. 

    This was actually already  in every .simrc file I could find (wasn't sure which one would take effect).

    I tried changing the pinorder of the auCdl and the symbol but it had no effect on the CDL netlist.   I even tried removing auCdlCDFPinCntrl=t and nothing changed.

  • Andrew Beckett
    in reply to kenc184

    Ken,

    You'll need to go to Tools->CDF->Edit in the CIW, pick "Base" and then edit the simulation information for the auCdl "simulator" for the digital IP cell. The approach that Rob mentioned will generate a default terminal order, but of course it may not match the order that is in the external file. You will need to change the termOrder in the auCdl simulation information to match the external file's order (the names need to match the symbol pin names, but the order must match that of the external file they correspond to).

    Andrew

  • RobMan
    in reply to Andrew Beckett

    Thanks Andrew, I was also going to add to double check the correct .simrc is loaded.

    .simrc File (Simulation Run Control)

    The .simrc file can be used by designers to customize simulation runs. This file enables designers to override the contents of the si.env file and set defaults for simulation variables which affect only their own simulations. The .simrc file is a way to set defaults on a per-user or per-system basis, and no other designer is affected by this file. This file is optional and is loaded if it exists. If you have not defined an entry for a global file, say .simrc, in the csflookupConfig file, then .simrc is searched for in the following order:

    • $SIMRC/.simrc
    • $ossSimUserSiDir/.simrc
    • dfII/local/.simrc
    • Current UNIX directory/.simrc
    • ~/.simrc
  • kenc184
    in reply to Andrew Beckett

    Thanks Andrew, that's the ticket.  Why though, does Cadence allow you to edit the pinorder through library manager only for it to have no effect?

  • Andrew Beckett
    in reply to kenc184
    kenc184 said:
    Why though, does Cadence allow you to edit the pinorder through library manager only for it to have no effect?

    That's news to me - I'm not aware of any way to edit the pin order through the library manager.

    There is the ability to set the port order in the schematic/symbol editor (maybe that's what you meant?) but that is only used by "digital" netlisters (i.e. not those controlled by CDF). In practice that's just the Verilog netlister (there's two long-standing modes which are kept for ancient legacy reasons as it's hard to disrupt flows).

    Andrew

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