LVS of a mixed signal design with a digital IP block?

I have finished the design and layout of an analog/mixed signal chip. There is a digital IP block to be included.  I can DRC and LVS the entire design successfully if the digital block is removed from the layout and the schematic. 

The symbol for the IP block is empty, it just indicates the top level connectivity. There is a .subckt for the IP block. So far, I have been unsuccessful in getting the  netlister to include a subckt call (of the X111 a b c d e ipblock type) in the netlist. 

There is no schematic for the IP block, just the symbol.

I suppose I could ask the ?IP designer to auto generate a schematic from verilog - I think it has that capability?

But is there a simple way to get the symbol to generate the subcircuit call in the netlist and simply include the netlist as a spice file in LVS?

As an example, I created a very simple case with the IP block, a standard cell, and a custom cell, then created a netlist with CIW>File>export>CDL.  I have fiddled with stop views and switch views to no avail.

As you can see, there is no mention of x274.