• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Liberate: Characterize integrated clock gating cell

Stats

  • Locked Locked
  • Replies 3
  • Subscribers 125
  • Views 6292
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Liberate: Characterize integrated clock gating cell

djupdal
djupdal over 2 years ago

Hi.

I have just made a clock gating cell and would like to characterize it with liberate.  However, liberate does not seem to understand it is a clock gater (resulting .lib does not include "clock_gating_integrated_cell" anywhere).  Is there anything extra I need to do to characterize a clock gating cell, or should it work just like for any other cell?  Other cells, like NAND, NOR, FF etc are all correctly identified automatically when I characterize them.

Are there any examples I can look at which include clock gating cells?

Best regards, Asbjørn

  • Cancel
Parents
  • Guangjun Cao
    Guangjun Cao over 2 years ago

    Hi Asbjørn,

    'clock_gating_integrated_cell' attribute can be added using set_attribute command or defined in a user_data file. Since it does not affect the characterization or is not simulation-related, Liberate does not automatically add such attributes.

    Regards,

    Guangjun

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • djupdal
    djupdal over 2 years ago in reply to Guangjun Cao

    Thanks, that was helpful. 

    I don't get any function specified for the output pin either.  Is that also something I should specify myself?

    I will do another characterization of my library now and see if I can get genus to recognize the clock gating cell when I specify the attribute manually.

    Regards,

    Asbjørn

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Guangjun Cao
    Guangjun Cao over 2 years ago in reply to djupdal

    Hi,

    clock-gating cells have a list of attributes at cell and pin levels. All need to be defined by users.

    Function of such cells is described by a statetable at cell level and state_function for output pins. 

    Please refer to Liberty User Guide that has some examples. if you already have a reference library, write out the user data file will the simplest way.

    Regards,

    Guangjun

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • Guangjun Cao
    Guangjun Cao over 2 years ago in reply to djupdal

    Hi,

    clock-gating cells have a list of attributes at cell and pin levels. All need to be defined by users.

    Function of such cells is described by a statetable at cell level and state_function for output pins. 

    Please refer to Liberty User Guide that has some examples. if you already have a reference library, write out the user data file will the simplest way.

    Regards,

    Guangjun

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information