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  3. Run transient with cmin option but applied to certain sub...

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Run transient with cmin option but applied to certain sub-circuits only?

StephanWeber
StephanWeber over 2 years ago

Hi,

I run schematic simulations, and see a dirty behavior if I use cmin=10f. So some nets are very sensitive to parasitic caps. Although the circuit is no high-speed circuit at all (so 10fF should not cause a problem).

However, as the circuit is large, it is hard to find the critical nets. One thing that may help is to have cmin only for certain blocks, is this possible?

Bye Stephan

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  • Andrew Beckett
    Andrew Beckett over 2 years ago

    Stephan,

    You can do this via the MTS interface these days - assuming that you're using a config for your test, go over the test name in Assembler, and Right Mouse→MTS Options. You'll see there that you can set cmin on specific cells or specific instances. That's the cleanest way in ADE, but it's also possible as a option statement (can be done via the additional arguments on the Simulation→Options→Analog form too (on the Miscellaneous tab) - see How to add cmin to specific instances or subcircuits during Spectre simulation?

    Andrew

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  • Andrew Beckett
    Andrew Beckett over 2 years ago

    Stephan,

    You can do this via the MTS interface these days - assuming that you're using a config for your test, go over the test name in Assembler, and Right Mouse→MTS Options. You'll see there that you can set cmin on specific cells or specific instances. That's the cleanest way in ADE, but it's also possible as a option statement (can be done via the additional arguments on the Simulation→Options→Analog form too (on the Miscellaneous tab) - see How to add cmin to specific instances or subcircuits during Spectre simulation?

    Andrew

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  • Andrew Beckett
    Andrew Beckett over 2 years ago in reply to Andrew Beckett

    I should also point out that cmin should really be a last resort - it normally suggests a problem with your device models.

    Andrew

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  • StephanWeber
    StephanWeber over 1 year ago in reply to Andrew Beckett

    Thanks for these hints! In my case the design was really very sensitive to parasitic caps, so post-layout simulation was giving unfortunately also a significant performance change. No problems on device models so far.

    Bye Stephan

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