Home
  • Products
  • Solutions
  • Support
  • Company

This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  • Products
  • Solutions
  • Support
  • Company
Community Custom IC Design Help on creating layout for a symmetric circuit by stitching...

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 125
  • Views 1341
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Help on creating layout for a symmetric circuit by stitching two "half-layout"

A1vis
A1vis over 1 year ago

Hi all.

Recently I was given a symmetric circuit and told to create a layout for it. Under my tutor's instruction, I removed half of the instances and created a half-circuit, from which I created a layout. Then in a new layout I imported the half-layout, mirrored it and stitched them together.

After some routing it could pass DRC and LVS check so I knew it's correct, but in the process of routing I found it annoying that all nets and (sub-)cells did not have any name, and I had to resort to my memory.

Following some instructions online I set both layout to transparent to establish device correspondence, but there weren't any change in the layout. New routing in the top level got their inferred name - but they were all wrong.

I'd like to ask what is the best practice of creating layout that takes the advantage of symmetry? Or maybe I should manually place the cells symmetrically?

  • Cancel
Parents
  • RobMan
    RobMan over 1 year ago

    You can consider the following..

     Cloning

    What Is Cloning? (Video) (cadence.com)

    Invoking and Using the Generate Clones Form (Video) (cadence.com)

    support.cadence.com/COSAgreementPage?artId=a1Od00000066MKhEAM&caseSessionKey=null&id=069d0000003Etg0AAC&sq=null

    Virtuoso Layout Suite XL: Connectivity Driven Editing User Guide -- Instance Cloning (cadence.com)

    Transparent instances

    support.cadence.com/COSAgreementPage?artId=a1O3w000009flfIEAQ&caseSessionKey=null&id=0693w00000DbxQGAAZ&sq=null

    Virtuoso Layout Suite XL: Connectivity Driven Editing User Guide -- Make Cell (cadence.com)

    In the scenario you describe you could make the 'half cell' a transparent instance and the binder will descend the hierarchy and update xl-compliance (instance and net binding).

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • A1vis
    A1vis over 1 year ago in reply to RobMan

    Sorry for the late reply... The previously inferred net name seems to be meddling with the binding process. I'm still trying these guides.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • A1vis
    A1vis over 1 year ago in reply to RobMan

    Sorry for the late reply... The previously inferred net name seems to be meddling with the binding process. I'm still trying these guides.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information