Community Custom IC Design Help on creating layout for a symmetric circuit by stitching...

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 125
  • Views 1341
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Help on creating layout for a symmetric circuit by stitching two "half-layout"

A1vis

Hi all.

Recently I was given a symmetric circuit and told to create a layout for it. Under my tutor's instruction, I removed half of the instances and created a half-circuit, from which I created a layout. Then in a new layout I imported the half-layout, mirrored it and stitched them together.

After some routing it could pass DRC and LVS check so I knew it's correct, but in the process of routing I found it annoying that all nets and (sub-)cells did not have any name, and I had to resort to my memory.

Following some instructions online I set both layout to transparent to establish device correspondence, but there weren't any change in the layout. New routing in the top level got their inferred name - but they were all wrong.

I'd like to ask what is the best practice of creating layout that takes the advantage of symmetry? Or maybe I should manually place the cells symmetrically?

Parents Reply Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.