Simulation temerature dependent on DC power

Martin,

You can do this with a Verilog-A module which is doing whatever measurement you wish (e.g. measuring the power) and then calling $cds_set_temperature (which is covered in the Cadence Verilog-A Language Reference manual).

Regards,

Andrew

Dear Andrew,

Another question:

It's easy to calculate the DC power on a branch with DC simulation in a Verilog-A model. With HB simulation, how to calculate the RF power on the RF output terminal and DC power on the VDD ternimal in a Verilog-A model?

Regards,

Martin

Hi Martin,

Two things:

1. You'd write the power measurement the same way - generally-speaking, you write Verilog-A code the same way (assuming time-domain) regardless of the analysis.
2. I'm not sure it makes sense that the temperature could change during the hb analysis anyway (the change would have to be periodic if it did - not even sure it's possible; temperature changes are normally rather longer time-constant than you'd be dealing with in an hb analysis). If it's going to change, it would have to do so during an initial tstab time (of course, you'd need to ensure that your Verilog-A doesn't have hidden states so that it can run in hb).

Andrew

Dear Martin,

I don't want to discourage you, but I honestly think you are not using the proper tool for this analysis. Basically, it appears your assumption is that the junction temperature you are using is related in some fashion to the junction temperature, assuming the change occurs instantaneously, and that the junction temperature is constant for all devices in your circuit.

However, I'm not sure what you are assuming for the theta (thermal resistance) and if you do use a value, it is implicitly assuming the power is even dissipated uniformly over your entire schematic netlist. This is not realistic as the power dissipated in a given component or trace is dependent on the power dissipated in that specific device, the theta of that device and the temperature of its layout environment.

There are tools that are more appropriate to this type of analysis that include both the simulation results and the layout. For example, an electromigration tool will perform this type of analysis and provide detailed information on the power dissipated in all devices, traces, and interconnects. Cadence, as well as other vendors, offer this type of analysis.

Once again, I don't want to discourage you Martin, and perhaps you are aware of the limitations I see with your methodology, but I wanted to at least mention it.

Shawn

Dear Shawn,

Thanks a lot. I will follow your advice to try other ways for this purpose. 

Regards,

Martin

Dear Martinsh,

First, I must apologize for addressing my prior post to you as "Martin" - I should have double-checked your name before writing my response! Sorry!

I think you are wise to consider using a tool designed specifically to study the impact of circuit power on performance and reliability. As a further reference if you are interested, Cadence's offering is outlined at URL:

https://community.cadence.com/cadence_blogs_8/b/cic/posts/virtuosity-moved-to-in-design-electromigration-analysis-yet

This URL includes a number of other links that might be of interest.

Good luck Martinsh!

Shawn

Dear Martinsh,

First, I must apologize for addressing my prior post to you as "Martin" - I should have double-checked your name before writing my response! Sorry!

I think you are wise to consider using a tool designed specifically to study the impact of circuit power on performance and reliability. As a further reference if you are interested, Cadence's offering is outlined at URL:

https://community.cadence.com/cadence_blogs_8/b/cic/posts/virtuosity-moved-to-in-design-electromigration-analysis-yet

This URL includes a number of other links that might be of interest.

Good luck Martinsh!

Shawn