Transition in conditional statement, VerilogAMS

Two things:

1. You could use transition in the statement where you are assigning VVout - provided that this is assigned outside of the conditional statement (so the transition is executed continuously)
2. You should really have the branches being the same in a switch branch like this (i.e. it should be I(Vout,n) rather than I(Vout).

You can't use the transition function to alter how it switches between a voltage and a current source if that's what you're asking (I'm not sure that would make a lot of sense).

Andrew

Thank you for your answer!
1-I didn't know transition could be used for a variable assignment, I don't think that's possible tho, given that even VVout is assigned in a conditional statement.
2- What kind of problem may this cause if I may ask?

I think I'll have to find another way to design the testbench without resorting to switching between current and voltage source. The brusque transitions without the use of "transition" is annoying in interpreting the results.

1. You could add another variable outside of the conditional statements:
   VVVout=transition(VVout,...);
   That would mean your VVout is assigned to conditionally, but you still have a transition. The transition can't be inside a conditional because it needs to be always executed so that it correctly handles the state transitions (sorry, that's probably a bit of a circular argument!)
2. It's not really a switch branch if the branches are different - I(Vout) is the current from Vout to ground, rather than V(Vout,n) which is between nodes Vout and n. What might happen is that something ends up floating when it's not connected the same way (for example, what happens to node n?). If node n is connected to the global ground, it may end up working fine - but you might end up with convergence difficulties. Switch branches are described in the Verilog AMS LRM, and also the Cadence Verilog A manual (see relevant pages attached from our manual)

switchbranch.pdf