How to override the default values using Verilog netlist.

Any suggestion or hint, please.

Omar Ghazal said:

Any suggestion or hint, please.

If this was urgent, you should contact customer support (this forum is responded to by people in their spare time). I didn't answer sooner because I was traveling and had no spare time.

Anyway, a couple of choices. First you could use the defparam approach you suggested:

`timescale 1ns / 1ns
module netlisting_500_schematic (clause, data);

inout [1:2] clause;
inout [1:4] data;


specify
specparam CDS_LIBNAME = "netlisting";
specparam CDS_CELLNAME = "netlisting_500_schematic";
specparam CDS_VIEWNAME = "schematic";
endspecify

vdoublerr I3 (.out(clause[2]), .in(data[4]));
vdoublerr I2 (.out(clause[2]), .in(data[3]));
vdoublerr I1 (.out(clause[1]), .in(data[2]));
vdoublerr I0 (.out(clause[1]), .in(data[1]));
defparam I0.parm1 = 100.0;
defparam I0.parm2 = 200.0;
defparam I0.parm3 = 300.0;
defparam I1.parm1 = 110.0;
defparam I1.parm2 = 210.0;
defparam I1.parm3 = 310.0;
defparam I2.parm1 = 120.0;
defparam I2.parm2 = 220.0;
defparam I2.parm3 = 320.0;
defparam I3.parm1 = 130.0;
defparam I3.parm2 = 230.0;
defparam I3.parm3 = 330.0;

endmodule

This creates a hierarchical property called "verilog" on each instance (which is not quite what you want). The good news is that you can fix it with SKILL as below.

The other way you can specify the parameters is on each instance line, but it seems this only works properly if you also define a placeholder for the doubler in Verilog (not Verilog-A) at the same time:

module vdoublerr (in, out);
input in;
output out;
parameter real parm1 = 0.2;
parameter real parm2 = 0.1;
parameter real parm3 = 5.0;


endmodule


`timescale 1ns / 1ns
module netlisting_500_schematic (clause, data);

inout [1:2] clause;
inout [1:4] data;


specify
specparam CDS_LIBNAME = "netlisting";
specparam CDS_CELLNAME = "netlisting_500_schematic";
specparam CDS_VIEWNAME = "schematic";
endspecify

vdoublerr #(.parm1(0.1),.parm2(0.4),.parm3(6.0)) I3 (.out(clause[2]), .in(data[4]));
vdoublerr #(.parm1(0.2),.parm2(0.5),.parm3(7.0)) I2 (.out(clause[2]), .in(data[3]));
vdoublerr #(.parm1(0.3),.parm2(0.6),.parm3(8.0)) I1 (.out(clause[1]), .in(data[2]));
vdoublerr #(.parm1(0.4),.parm2(0.7),.parm3(9.0)) I0 (.out(clause[1]), .in(data[1]));


endmodule

This SKILL code can then be used (for both cases):

procedure(CCFmoveVerilogParams(@optional (cv geGetEditCellView()))
  foreach(inst cv~>instances
    when(dbFindProp(inst "verilog")
      foreach(prop dbFindProp(inst "verilog")~>value
        putprop(inst prop~>value prop~>name)
      )
      dbDeletePropByName(inst "verilog")
    )
  )
  schCheck(cv)
  dbSave(cv)
)

Simply open the netlisting_500_schematic schematic and run CCFmoveVerilogParams(). I found a few requests to provide a way to directly import the parameters rather than to this verilog hierProp, but it's never been implemented.

Andrew

Omar Ghazal said:

Any suggestion or hint, please.

If this was urgent, you should contact customer support (this forum is responded to by people in their spare time). I didn't answer sooner because I was traveling and had no spare time.

Anyway, a couple of choices. First you could use the defparam approach you suggested:

`timescale 1ns / 1ns
module netlisting_500_schematic (clause, data);

inout [1:2] clause;
inout [1:4] data;


specify
specparam CDS_LIBNAME = "netlisting";
specparam CDS_CELLNAME = "netlisting_500_schematic";
specparam CDS_VIEWNAME = "schematic";
endspecify

vdoublerr I3 (.out(clause[2]), .in(data[4]));
vdoublerr I2 (.out(clause[2]), .in(data[3]));
vdoublerr I1 (.out(clause[1]), .in(data[2]));
vdoublerr I0 (.out(clause[1]), .in(data[1]));
defparam I0.parm1 = 100.0;
defparam I0.parm2 = 200.0;
defparam I0.parm3 = 300.0;
defparam I1.parm1 = 110.0;
defparam I1.parm2 = 210.0;
defparam I1.parm3 = 310.0;
defparam I2.parm1 = 120.0;
defparam I2.parm2 = 220.0;
defparam I2.parm3 = 320.0;
defparam I3.parm1 = 130.0;
defparam I3.parm2 = 230.0;
defparam I3.parm3 = 330.0;

endmodule

This creates a hierarchical property called "verilog" on each instance (which is not quite what you want). The good news is that you can fix it with SKILL as below.

The other way you can specify the parameters is on each instance line, but it seems this only works properly if you also define a placeholder for the doubler in Verilog (not Verilog-A) at the same time:

module vdoublerr (in, out);
input in;
output out;
parameter real parm1 = 0.2;
parameter real parm2 = 0.1;
parameter real parm3 = 5.0;


endmodule


`timescale 1ns / 1ns
module netlisting_500_schematic (clause, data);

inout [1:2] clause;
inout [1:4] data;


specify
specparam CDS_LIBNAME = "netlisting";
specparam CDS_CELLNAME = "netlisting_500_schematic";
specparam CDS_VIEWNAME = "schematic";
endspecify

vdoublerr #(.parm1(0.1),.parm2(0.4),.parm3(6.0)) I3 (.out(clause[2]), .in(data[4]));
vdoublerr #(.parm1(0.2),.parm2(0.5),.parm3(7.0)) I2 (.out(clause[2]), .in(data[3]));
vdoublerr #(.parm1(0.3),.parm2(0.6),.parm3(8.0)) I1 (.out(clause[1]), .in(data[2]));
vdoublerr #(.parm1(0.4),.parm2(0.7),.parm3(9.0)) I0 (.out(clause[1]), .in(data[1]));


endmodule

This SKILL code can then be used (for both cases):

procedure(CCFmoveVerilogParams(@optional (cv geGetEditCellView()))
  foreach(inst cv~>instances
    when(dbFindProp(inst "verilog")
      foreach(prop dbFindProp(inst "verilog")~>value
        putprop(inst prop~>value prop~>name)
      )
      dbDeletePropByName(inst "verilog")
    )
  )
  schCheck(cv)
  dbSave(cv)
)

Simply open the netlisting_500_schematic schematic and run CCFmoveVerilogParams(). I found a few requests to provide a way to directly import the parameters rather than to this verilog hierProp, but it's never been implemented.

Andrew

Thank you So much  it worked .