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Create schematic from netlist(verilog)

SimhanAnalog

I am looking to create a schematic from a netlist(verilog) file. The verilog file just has connections of different modules. It doesnt have any logic(behaviouiral verilog code).

Example:
Say I have a cell sample_core which has a symbol view. Among other input and output ports it also has 4 outputs o_w,o_x,o_y,o_z each 7:0.
I want to create a sample_wrap cell which does some rewiring of sample_core. But I dont want to do it manually in schematic. So I will create a verilog file that does the rewiring and want to generate a schematic and symbol views from the verilog. Example given below.  This verilog file I will generate using some script to avoid mistakes.


module sample_wrap

(

//some many other inputs and outputs

output [3:0] o_a,

output [3:0] o_b,

output [3:0] o_c,

output [3:0] o_d,

output [3:0] o_e,

output [3:0] o_f,

output [3:0] o_g,

output [3:0] o_h

);

sample_core I_sample_core

(

//some many other inputs and outputs

.o_w({o_h[0],o_g[0],o_f[0],o_e[0],o_d[0],o_c[0],o_b[0],o_a[0]}),

.o_x({o_h[1],o_g[1],o_f[1],o_e[1],o_d[1],o_c[1],o_b[1],o_a[1]}),

.o_y({o_h[2],o_g[2],o_f[2],o_e[2],o_d[2],o_c[2],o_b[2],o_a[2]}),

.o_z({o_h[3],o_g[3],o_f[3],o_e[3],o_d[3],o_c[3],o_b[3],o_a[3]}),

);

endmodule

Parents

  • Did you have a question? You can use File→Import→Verilog in Virtuoso to import the verilog and create a schematic, if that is what you meant to ask.

    Andrew.

  • in reply to Andrew Beckett

    Yes. This is what I was looking for. Thanks. One observation is that the import verilog option doesnt support system verilog construct. Like if my sample_wrap.sv file had the following

    module sample_wrap

    (

    //some many other inputs and outputs

    output logic [3:0] o_a,

    output logic [3:0] o_b,

    output logic [3:0] o_c,

    output logic [3:0] o_d,

    output logic [3:0] o_e,

    output logic [3:0] o_f,

    output logic [3:0] o_g,

    output  logic [3:0] o_h

    );

    sample_core I_sample_core

    (

    //some many other inputs and outputs

    .o_w({o_h[0],o_g[0],o_f[0],o_e[0],o_d[0],o_c[0],o_b[0],o_a[0]}),

    .o_x({o_h[1],o_g[1],o_f[1],o_e[1],o_d[1],o_c[1],o_b[1],o_a[1]}),

    .o_y({o_h[2],o_g[2],o_f[2],o_e[2],o_d[2],o_c[2],o_b[2],o_a[2]}),

    .o_z({o_h[3],o_g[3],o_f[3],o_e[3],o_d[3],o_c[3],o_b[3],o_a[3]}),

    );

    endmodule

    It says import failed since it doesnt recognize the "logic" term. Is there some flag that we can give to the tool to recognize this?

Reply
  • in reply to Andrew Beckett

    Yes. This is what I was looking for. Thanks. One observation is that the import verilog option doesnt support system verilog construct. Like if my sample_wrap.sv file had the following

    module sample_wrap

    (

    //some many other inputs and outputs

    output logic [3:0] o_a,

    output logic [3:0] o_b,

    output logic [3:0] o_c,

    output logic [3:0] o_d,

    output logic [3:0] o_e,

    output logic [3:0] o_f,

    output logic [3:0] o_g,

    output  logic [3:0] o_h

    );

    sample_core I_sample_core

    (

    //some many other inputs and outputs

    .o_w({o_h[0],o_g[0],o_f[0],o_e[0],o_d[0],o_c[0],o_b[0],o_a[0]}),

    .o_x({o_h[1],o_g[1],o_f[1],o_e[1],o_d[1],o_c[1],o_b[1],o_a[1]}),

    .o_y({o_h[2],o_g[2],o_f[2],o_e[2],o_d[2],o_c[2],o_b[2],o_a[2]}),

    .o_z({o_h[3],o_g[3],o_f[3],o_e[3],o_d[3],o_c[3],o_b[3],o_a[3]}),

    );

    endmodule

    It says import failed since it doesnt recognize the "logic" term. Is there some flag that we can give to the tool to recognize this?

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