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ADE Schemetic simulation will not auto re-netlist Verilog-A Module

SimbaG

When I edit the Verilog-A module which referred in schemetic, the ADE simulation environment will not auto-update the netlist until I open the Verilog-A module -> Extract.

Seems like the Spectre will refer to the netlist.oa file rather than the .va file in the netlist cell view.

Is there a work around that auto update it? Should I consider use config view to do so?

Parents

  • Spectre doesn't look at the netlist.oa - that will however impact the incremental netlist, so it's possible that it won't notice parameter or pin name changes etc and the instance won't get renetisted. Since however the netlist includes the path to the veriloga.va I wouldn't expect it to look at anything else. 

    Without knowing the specifics of what is going wrong, it's hard to say, but you quite frankly should never directly edit the file. That's not a supported flow.

    Andrew

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  • Spectre doesn't look at the netlist.oa - that will however impact the incremental netlist, so it's possible that it won't notice parameter or pin name changes etc and the instance won't get renetisted. Since however the netlist includes the path to the veriloga.va I wouldn't expect it to look at anything else. 

    Without knowing the specifics of what is going wrong, it's hard to say, but you quite frankly should never directly edit the file. That's not a supported flow.

    Andrew

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