Characterizing cells with verilog-A models by liberate, but the model or instance can not be found

Is the the 'nmos' modeled as verilogA? if not, this may not necessarily be related to verilogA model being used, as what the title suggested.

Instance name starting 'M' is considered as a leacell model. You may try to add 'x' prefix to all instances that have name prefix of M/D/N/P/R(unless parasitic R). A possible alternative is to add -element option to your define_leafcell command, when these prefix is used.

A non-cmos design may not be supported for automatic arc recognition. You need to use define_arc/define_leakage for all arcs you want to characerize. -user_arcs_only option can also be added to char_library command in such a case.

Regards,

Guangjun

I forgot to ask which device/type is modeled as VerilogA. This device should also be declared as a leafcell. for example, a diode with VerilogA model needs these command,

set_var extsim_deck_header ".hdl /support/diode.va"

define_leafcell -extsim_model -type diode\
-pin_position {0 1} {diodeva}

here, -extsim_model option is required.

Guangjun

thank you for your reply so much.

our MOSFET(nmos) is modeled as verilogA, not a  diode,but I still add  the command to try, It doesn't seem do anything

set_var extsim_deck_header " .hdl $rundir/MODELS/veriloga.va"

when I add -element option as follow, The same error still exists

define_leafcell -element -type nmos -pin_position {0 1 2 3} {nch}

but when I add 'x' prefix to all instances, there is a new error

log;

*Info* : Initializing SKI environment...
Initializing Spice
*Info* No global model has been read in. Will expect model defined inside instance.
Building library database
ERROR (LIB-203): (char_library): Cell 'INVD1' is scheduled for characterization but has no netlist, has an empty subckt or has no port on the subckt. This cell will be skipped. Check the netlist and rerun.
WARNING (LIB-961): (char_library): Leakage deck initialization was requested using '.ic', but the 'leakage_sim_duration' was set to '0'. This may lead to unexpected leakage characterization results. Change 'leakage_sim_duration' to a positive non-zero value in seconds or change the setting of 'set_sim_init_condition' and rerun.
MEM=2476 MB
MEM=2476 MB
MEM=2476 MB

*Info* (char_library) : SKI process child signal handler disabled.

MEM=2509 MB
Performance statistics (96 thread(s)):
Spectre cpu time = 0.00 hours (0.00 seconds)
Total PreProcessing time = 0.00 hours (0.00 seconds)
Total cpu time = 0.00 hours (0.00 seconds)
Wall clock time = 0.00 hours (1.00 seconds)

Characterization finished at Fri Jan 17 18:30:45 2025

Characterization statistics:

Number of cells to characterize = 1
Number of define_cell commands = 1
Number of passing cells = 0
Number of failing cells = 0
List of failing cells {}
Number of skipped cells = 1
List of skipped cells {INVD1}

Finished Liberate Execution.
Updating library database /homes/RuiLi/liberate/file/liberate/LDB/example.ldb.4.gz
Memory usage: 2484 Mbytes

LIBERATE parameter "mx_format_expand_buses" set to "0"
LIBERATE parameter "ecsm_multi_stage_cap_mode" set to "0"
LIBERATE parameter "ccsp_mode" set to "0"
LIBERATE parameter "ecsm_waveform_error_adjust" set to "0x2"
WARNING (LIB-989): (write_library): This command will be skipped because there is no cell data to write. Characterize or read the cell data and rerun.
WARNING (LIB-989): (write_library): This command will be skipped because there is no cell data to write. Characterize or read the cell data and rerun.
Writing datasheet in text format to /homes/RuiLi/liberate/file/liberate/DATASHEET/example.txt
*Error* (write_datasheet) : No cell groups found in the library /homes/RuiLi/liberate/file/liberate/DATASHEET/example

As I said, -extsim_model option is needed for leaf cells with verilogA model. My diode example is just an example that can be applied to other devices. 

for your nmos, 

define_leafcell -extsim_model  -type nmos -pin_position {0 1 2 3} {nch}

Also, try with/without the verilogA mode in your extsim_model_include and read_spice. You probably should not include it, as it has been defined in extsim_deck_header.

You have not clarified whether you have user-defined define_arc command. Liberate may not be capable of automatically generate arcs/vectors with designs that are not CMOS based. The sitution is not clear, if your design has only devices with verilogA model.

If the above settings do not work, please contact customer support with a  full test case. 

Guangjun 

I'm sorry I overlooked -extsim_model option before, I have added this option as suggested，and also define arcs in template.tcl. as follow;

" try with/without the verilogA mode in your extsim_model_include and read_spice"

(According to my understanding, just remove these two lines

#set_var extsim_model_include $rundir/MODELS/section_mos.scs

#set spicefiles $rundir/MODELS/section_mos.scs

but what about read_spice? I don't understand，

“read_spice $spicefiles”  seems can not be removed.),,

it shows the same error as before.

the log and template file as follows

template.tcl:

if {[ALAPI_active_cell "INVD1"]} {
define_cell \
-input { I } \
-output { ZN } \
-pinlist { I ZN} \
-delay delay_template_5x5 \
-power power_template_5x5 \
INVD1

define_leakage -when "(I * !ZN)" INVD1
define_leakage -when "(!I * ZN)" INVD1

# delay arcs from I => ZN negative_unate combinational
define_arc \
-vector {FR} \
-related_pin I \
-pin ZN \
INVD1

# delay arcs from I => ZN negative_unate combinational
define_arc \
-vector {RF} \
-related_pin I \
-pin ZN \
INVD1

log:

LIBERATE parameter "slew_lower_rise" set to "0.3"
LIBERATE parameter "slew_upper_rise" set to "0.7"
LIBERATE parameter "slew_lower_fall" set to "0.3"
LIBERATE parameter "slew_upper_fall" set to "0.7"
LIBERATE parameter "measure_slew_lower_rise" set to "0.3"
LIBERATE parameter "measure_slew_upper_rise" set to "0.7"
LIBERATE parameter "measure_slew_lower_fall" set to "0.3"
LIBERATE parameter "measure_slew_upper_fall" set to "0.7"
LIBERATE parameter "max_transition" set to "1.5e-09"
LIBERATE parameter "extsim_deck_header" set to " .hdl /homes/RuiLi/liberate/file/liberate/MODELS/veriloga.va"
INFO (LIB-511): (define_leafcell): Leafcell 'nch' (instance) has been identified with pin_position (0 1 2 3) mapped to (D G S B).
LIBERATE parameter "extsim_exclusive" set to "1"
LIBERATE parameter "spectre_pwr" set to "0"
LIBERATE parameter "simulator" set to "ski"
LIBERATE parameter "char_library_skip_var_list" set to ""
Start Characterizing Library at (Fri Jan 17 22:45:26 CST 2025)

*Info* Removing all types
*Info* Max Shared Memory Segments : 4096
*Info* No unattached Shared Memory Segments belonging to RuiLi out of 441 total.
*Info* Max Semaphore Arrays : 128
*Info* No unattached Semaphore Arrays belonging to RuiLi out of 1 total.
*Info* Max Message Queues : 32000
*Info* No Message Queues
*Info* Zombie Process 'lsb_release' isn't 'spectre' related. Skipping.
*Info* Zombie Process 'whoami' isn't 'spectre' related. Skipping.
*Info* Zombie Process 'lsb_release' isn't 'spectre' related. Skipping.
*Info* Zombie Process 'whoami' isn't 'spectre' related. Skipping.
WARNING (LIB-103): When using Spectre-SKI, runtime may significantly improve when using an extsim_model_include/define_leafcell flow. This is needed to enable the Spectre modellib flow.
WARNING (LIB-909): (read_spice): Could not find a model/subckt definition for instance 'XM0' named 'MoS2FET' with '3' terminals. Liberate will attempt to guess the device type. Read the models in read_spice or use define_leafcell to map the name to a model/subckt and rerun.
WARNING (LIB-933): To enable automatic leaf-cell recognition, the variable 'extsim_model_include' is required.
WARNING (LIB-1007): (char_library): This LIBERATE release was qualified with MMSIM version '18.1.0.235.isr3' but older version '15.1.0.284.isr1' was detected. Older versions of MMSIM are not recommended. Update to the qualified MMSIM version and re-run.
INFO (LIB-956): (read_spice): Reading file: '/homes/RuiLi/liberate/file/liberate/NETLIST/INVD1.sp'.
INFO (LIB-940): The parser has identified the following leaf cells. Review these for missing or incorrect settings and if needed, add them to your Tcl script and rerun.
INFO (LIB-906): (AUTO): define_leafcell -type black_box -pin_position {0 1 2 3} INVD1
INFO (LIB-907): (AUTO): define_leafcell -element -type black_box -pin_position {0 1 2} MoS2FET
INFO (LIB-943): Finished reading netlist(s) at Jan 17 22:45:27.
INFO (LIB-711): Feature 'Spectre_char_opt' exists in the license pool. The parameter 'spectre_use_char_opt_license' will be set to '1'.
*Info* (char_library) : SKI process child signal handler enabled.

INFO (LIB-966): Using Spectre version 15.1.0.284.isr1 located at: /opt/cadence/MMSIM151/bin/spectre.
*Info* Use temporary directory '/homes/RuiLi/liberate/file/liberate'.
LIBERATE parameter "extsim_deck_dir" defaulted to sanjose:/homes/RuiLi/liberate/file/liberate/decks.sanjose.T20250117224524081610S0063769

*Info* : Initializing SKI environment...
Initializing Spice
*Info* No global model has been read in. Will expect model defined inside instance.
Building library database
ERROR (LIB-203): (char_library): Cell 'INVD1' is scheduled for characterization but has no netlist, has an empty subckt or has no port on the subckt. This cell will be skipped. Check the netlist and rerun.
WARNING (LIB-961): (char_library): Leakage deck initialization was requested using '.ic', but the 'leakage_sim_duration' was set to '0'. This may lead to unexpected leakage characterization results. Change 'leakage_sim_duration' to a positive non-zero value in seconds or change the setting of 'set_sim_init_condition' and rerun.
MEM=2475 MB
MEM=2475 MB
MEM=2475 MB

*Info* (char_library) : SKI process child signal handler disabled.

MEM=2508 MB
Performance statistics (96 thread(s)):
Spectre cpu time = 0.00 hours (0.00 seconds)
Total PreProcessing time = 0.00 hours (0.00 seconds)
Total cpu time = 0.00 hours (0.00 seconds)
Wall clock time = 0.00 hours (1.00 seconds)

Characterization finished at Fri Jan 17 22:45:29 2025

Characterization statistics:

Number of cells to characterize = 1
Number of define_cell commands = 1
Number of passing cells = 0
Number of failing cells = 0
List of failing cells {}
Number of skipped cells = 1
List of skipped cells {INVD1}

Finished Liberate Execution.
Updating library database /homes/RuiLi/liberate/file/liberate/LDB/example.ldb.12.gz
Memory usage: 2483 Mbytes

LIBERATE parameter "mx_format_expand_buses" set to "0"
LIBERATE parameter "ecsm_multi_stage_cap_mode" set to "0"
LIBERATE parameter "ccsp_mode" set to "0"
LIBERATE parameter "ecsm_waveform_error_adjust" set to "0x2"
WARNING (LIB-989): (write_library): This command will be skipped because there is no cell data to write. Characterize or read the cell data and rerun.
WARNING (LIB-989): (write_library): This command will be skipped because there is no cell data to write. Characterize or read the cell data and rerun.
Writing datasheet in text format to /homes/RuiLi/liberate/file/liberate/DATASHEET/example.txt
*Error* (write_datasheet) : No cell groups found in the library /homes/RuiLi/liberate/file/liberate/DATASHEET/example
Peak memory usage: 2.45 GB
Peak virtual memory usage: 1.45 GB
Peak physical memory usage: 0.99 GB
Wall time : 0.00 hours (5.00 seconds)
LIBERATE exited on sanjose at Fri Jan 17 22:45:29 2025

I wonder if something else should I add to char.tcl to load a external  verilogA model to liberate. it seems model cannot be recognized.

I think this discuss is Similar to my situation，but the error is different.It's a pity

 Characterizing library for emerging 2DFETs with in-house .va based models 

The documentation on extsim_model_include, read_spice adn define_leafcell is quite clear. 

given your first script, try the following changes,

1. add x to all your M/D/R/C/N/P* instances of MOS/Diode/Res/Cap/BJTs

2. define_leacell for nmod, define_leafcell -extsim_model  -type nmos -pin_position {0 1 2 3} {nch}. make sure the pin order in your model file is DGSB.

The latest logfile indicates you have another device, MoS2FET. Does this device have a spice model that is included in file 'section_mos.scs'? If it is a 3-terminal MOSFET, eg. B-S shorted, then try -pin_position {0 1 2 2}.

3. keep your set_var extsim_deck_header ".hdl /support/diode.va"

4. remove va model from 'section_mos.scs', if it is included. Then keep extsim_model_include and read_spice .

5. you need -user_arcs_only for char_library command

6. you may need '-extsim spectre' in char_library command. try this only if all above still do not work

If the characterization still does not run, please raise a Case with Cadence customer support. It will also save you time to fully explain your case.

Regards,

Guangjun