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Stability Analysis of a Ramp Generator Circuit in Integration Phase

baltaci

Dear Cadence Community,

I am a user of IC23.1.

I am designing a ramp generator circuit that operates in two phases, controlled by non-overlapping clock signals ϕ1 and ϕ2. Below is a schematic representation of the circuit:

Behaviour:

  • When ϕ1 = 1, a switch shorts the feedback capacitor, and the opamp operates as a unity-gain buffer.
  • When ϕ2 = 1, the switch controlled by ϕ1 is open, and the only feedback element is the capacitor. A constant current source is connected to the inverting input of the opamp, generating a linearly increasing ramp at the output.

Stability Analysis Concern

For the case when ϕ1 = 1, stability analysis is straightforward because the circuit behaves as a unity-gain buffer. Running an STB analysis in this case is simple.

However, for the case when ϕ2 = 1, stability analysis presents several challenges:

  • The circuit has no single DC operating point due to the ramp behavior.
  • A standard DC analysis would likely result in the opamp output saturating to the power supply, which is not useful for stability analysis.
  • My problem is that I do not even know how to run a single stability analysis during this phase (ϕ2 = 1) because the STB analysis would not be run at a DC operating point that one would be interested in, since it is not a stable DC operating point.

The equivalent circuit for the ϕ2 = 1 phase is shown below:

What is the recommended methodology to perform a stability analysis in such situations?

I appreciate any guidance or insights on this topic.

Best regards,
Can

  • Usually you would use pss (to simulate a period of operation of your clocks) and then pstb to give you the time-averaged loop gain of the amplifier, from which you can assess the stability. Then you are not dependent upon the instantaneous DC operating point, but a time-varying operating point.

    Andrew

  • in reply to Andrew Beckett

    Andrew,

    Thank you very much for your response.

    I had already performed the PSS and PSTB analyses as you suggested. However, the results I obtained did not provide much intuition regarding the circuit's stability.

    To clarify my concerns, I would like to attach some screenshots of the gain and phase curves from the PSTB analysis.



    When I zoom around the low frequencies:


    STB analysis when phi1 = 1 (these curves are quite understandable considering the analysis of the circuit):


    One of my main questions is regarding the definition of the "time-averaged loop gain of the amplifier." Does this mean that the STB analysis is performed at multiple points within one period, and then the average gain and phase are taken?

    If this is the case, I am concerned about whether the PSTB analysis reliably ensures that each phase within one period has a sufficiently large phase and gain margin. Specifically:

    • My circuit might exhibit very poor stability during a specific phase that lasts very short w.r.t. one period (ex: only 0.1% of the entire period), while the rest remains stable. Given how short this unstable phase is (or phase with very low phase margin), could it be lost or diluted when averaging the gain and phase over the entire period?
    • Additionally, there may be phases where the circuit is idle (e.g., when it is switched off or has zero gain for some reason). Could these irrelevant loop gain values affect the overall interpretation of stability, potentially causing the unstable parts to be lost in the information obtained from the analysis?
    • Wouldn't it be more useful to analyze stability separately for each phase of the circuit rather than averaging over the entire period? Isn't there another methodology that enables us to use such an approach?

    Moreover, I have also read some of the available sources on PSTB analysis, including forum discussions and the user manual, but I still do not fully understand what happens behind the scenes. For example, the working principles of tran, stb, dc, and ac analyses are quite clear, but this is not the case for PSTB analysis. If you have any recommended sources that provide a deeper, step-by-step explanation of how the algorithm works, I would greatly appreciate it.

    Thank you in advance for your guidance.

    Best regards,
    Can

  • in reply to baltaci
    baltaci said:

    Moreover, I have also read some of the available sources on PSTB analysis, including forum discussions and the user manual, but I still do not fully understand what happens behind the scenes. For example, the working principles of tran, stb, dc, and ac analyses are quite clear, but this is not the case for PSTB analysis. If you have any recommended sources that provide a deeper, step-by-step explanation of how the algorithm works, I would greatly appreciate it.

    PSTB is related to STB just like PAC is related to AC analysis. So you might take a look at support.cadence.com/.../techpubDocViewerPage or at section 4.2 of designers-guide.org/.../rf-sim.pdf

  • Hi,

    the circuit is an integrator. If input is not periodic but e.g. fix, a non-periodic output will be present, but still stability can be checked. Run Transient, and use actimes
    & acnames (=stb) feature (best for different phases). This will check the stability of the integrator alone, so you get e.g. the phase margin for the op-amp.

    If the system is more complex like forming an SC filter, go for pss+pstb analyses.

    Bye Stephan

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