Import verilog with VDD, VSS, VNW & VPW

Hi,

what do you mean with "VDD, VSS, VNW & VPW ports are unconnected in the schematic view"? Do you just mean the pin is missing or is any of the impoted cells unconnected?

Some general words:

- When I import Verilog netlists, I don't see any "VDD" or "VSS" nets or terminals either, which is normal (for the technology we use). Connection exists anyways, by (inheritable)  global nets as defined in the standard cells.There is no need for me to modify Verilog code to insert any power nets.

- When using an instance of a cell imported as Verilog netlist, I can assign the power supply I want by using user proerties of type "netSet". I simply define the correct poperty name of the inherited global net (e.g. "ground_gnd" and assign the correct net name "e.g. "vssd"). This even works if there is a hierarchy of imported cells, by simply assigning the "netSet" user property on the most top cell of such hierarchy, as all cells on this and all levels below simply inherit this connection.

- When doing layout, power nets do exist, although invisible in the schematics, as they are actually there in the schematics as a global net.

- The "Global Net Options" of the VerilogIn tool allow you to define global net names and also to create net expressions.Maybe this helps.

Okay, I need to edit my post, as I cannot reply to your answer. So here is my reply:

Hi,

okay, if you need to add these connections for VDD and VSS, then "netSet" is the right way, as this keeps the symbol of functional view and schematic view in synchronization.

If you can see the schematic symbol of the instance defining the global net (like a "vdd" instance of the fab's primitive devices library or vdd_inherit of Cadence analogLib), click on the pin of this instance and open the property dialog. There, you will find "Property Name", and tihs is the one to use for a netSet. (For vdd_inherit of Cadence, the Property Name is simply "vdd".)

To add the net set, open the properties of your top instance of the digital circuit, click the "Add" button and select Type "netSet". Enter the property name you found in the "Name" field and enter the net name of the supply net in your schematics containing the digital circuits instance in the "Value" field, then click OK and repeat this for the second supply net.

(The cell may also use simple pins with such properties, but this does not change the way you can assign a net by adding a netSet property.)

VNW and VPW do not exist in the design flow I am familiar with, so I need to guess that these two are separate supplies for "NWELL" and "PWELL", or, if you have a dual-supply design, the second voltage domain?

In the process I use, there is a level shifter with two supply domains, which uses simple schematic pins ON THE SCHEMATIC to define the supply voltage, but the pins have no pin equivalent on the symbol virew. Yet, they are "hidden pins". Such pins have a "Net Expression" attached.  If you have pins like that for VHW and VPW, then you can also use the netSet property. (Click on the pin in the schematic (if required, go to down to the most bottom level of the stadard cell, it can be, that you don't see it elsewhere but there, display its properties and lok for its Property Name).

Does that help? Maybe you can describe in more detail how the VNW adn VPW nets are represented in your circuit. And do descend down the hierarchy to see if there is a hidden pin at one of the hierarchy levels...

If it is a well contact, then there may be the need for an extra standard cell (well tap cell) to be added. In a digital design flow inclucing layout, the PNR tool takes care of this (obeying the rules of a sufficiently large number and maximum distance to meet latchup protection rules). Such well tap cells then do the connection of the wells to VDD and VSS automatically. So maybe you use a process with tapless standard cells and you simply need to add those tap cells?

Hi Volker,

Thank you for your response. By  "VDD, VSS, VNW & VPW ports are unconnected in the schematic view" I indeed mean the pins are missing, which is normal for digital flow as verilog functional view does not have those pins defined. However, for AMS simulations with synthesized schematic, I need to add those connections. As far as inherited nets are concerned, I see VDD and VSS defined as inherited nets in the standard cells but VNW and VPW are not defined as inherited nets. So, the main query is how to define connections to VNW and VPW at top level.

Hi Volker,

Thank you for your response. By  "VDD, VSS, VNW & VPW ports are unconnected in the schematic view" I indeed mean the pins are missing, which is normal for digital flow as verilog functional view does not have those pins defined. However, for AMS simulations with synthesized schematic, I need to add those connections. As far as inherited nets are concerned, I see VDD and VSS defined as inherited nets in the standard cells but VNW and VPW are not defined as inherited nets. So, the main query is how to define connections to VNW and VPW at top level.

Hi,

okay, if you need to add these connections for VDD and VSS, then "netSet" is the right way, as this keeps the symbol of functional view and schematic view in synchronization.

If you can see the schematic symbol of the instance defining the global net (like a "vdd" instance of the fab's primitive devices library or vdd_inherit of Cadence analogLib), click on the pin of this instance and open the property dialog. There, you will find "Property Name", and tihs is the one to use for a netSet. (For vdd_inherit of Cadence, the Property Name is simply "vdd".)

To add the net set, open the properties of your top instance of the digital circuit, click the "Add" button and select Type "netSet". Enter the property name you found in the "Name" field and enter the net name of the supply net in your schematics containing the digital circuits instance in the "Value" field, then click OK and repeat this for the second supply net.

(The cell may also use simple pins with such properties, but this does not change the way you can assign a net by adding a netSet property.)

---

VNW and VPW do not exist in the design flow I am familiar with, so I need to guess that these two are separate supplies for "NWELL" and "PWELL", or, if you have a dual-supply design, the second voltage domain?

In the process I use, there is a level shifter with two supply domains, which uses simple schematic pins ON THE SCHEMATIC to define the supply voltage, but the pins have no pin equivalent on the symbol virew. Yet, they are "hidden pins". Such pins have a "Net Expression" attached.  If you have pins like that for VHW and VPW, then you can also use the netSet property. (Click on the pin in the schematic (if required, go to down to the most bottom level of the stadard cell, it can be, that you don't see it elsewhere but there, display its properties and lok for its Property Name).

Does that help? Maybe you can describe in more detail how the VNW adn VPW nets are represented in your circuit. And do descend down the hierarchy to see if there is a hidden pin at one of the hierarchy levels...

---

If it is a well contact, then there may be the need for an extra standard cell (well tap cell) to be added. In a digital design flow inclucing layout, the PNR tool takes care of this (obeying the rules of a sufficiently large number and maximum distance to meet latchup protection rules). Such well tap cells then do the connection of the wells to VDD and VSS automatically. So maybe you use a process with tapless standard cells and you simply need to add those tap cells?