Import verilog with VDD, VSS, VNW & VPW

Please see my first reply that I have edited in the meanwhile. I had some trouble responding to your answer, so you find my latest reply there.

I think the key point is to check if you use a tapless standard cell process (see last paragraph of my edited text).

Thank you very much Volker. The way you mentioned worked for all of the ports I wanted to connect (VDD, VSS, VNW & VPW). VNW and VPW are indeed connections to NWELL and PWELL. 

Perfect.

Unless you only need this solution for first simulation and you will later use a proper place and route tool that automatically adds the well tap cells, please don't forget to add them manually to also have them in your layout...

If you do use a proper place and route tool, it will generate a new Verilog netlist for the routed design anyways, then including the well tap cells and all the additional buffers and antenna cells that the tool identifies to be required and inserted to get a working layout meeting timing constraints. Then, you should import that netlist instead of the pre-layout Verilog netlist and eventually re-simulate.

Sure, will do that.
Thank you very much once again.

Hello Volker,

When I simulated I found out that VPW and VNW do not have "Property Name" attribute. In that case how can we use netSet property?

Thanks

Hello Volker,

When I simulated I found out that VPW and VNW do not have "Property Name" attribute. In that case how can we use netSet property?

Thanks

Again, I can only guess.

Presumably, the most easy thing is to simply add a tap cell from your standard cell library into the test bench you use for simulation.

If you are lucky, the tap cell has a VDD and VSS pin (or property name you can use in conjunction with a netSet for VDD / VSS), and then simply connects VPW / VNW to VDD and VSS, respectively, by itself, using a global net of whatever name.

Otherwise, investigate the global net names of VPW and VNW (like e.g. "vpw!" and "vwn!") and assign suitable voltages to the two global nets in your test bench directly by e.g. two DC voltage sources.