Verilog A VACOMP-2032: Parameter for port width leads to error.

Hi,

you simply need to define the electrical net to have the same size.

Instead of writing

electrical in, out ;

you should write

electrical in ;

electrical [0:bits-1] out ;

EDIT:

And by the way, I am not sure if "bits" may be specified as a parameter (it will be tough to keep that in sync with the symol).

If it does not work as a parameter, use a macro instead:

`include "constants.vams"
`include "disciplines.vams"

`define bits 8

module adc(in,out);

    parameter fullscale=1.0, delay=0.0, ttime=10n ;
    input in ;
    output [0:`bits-1] out ;

    electrical in ;
    electrical [0:`bits-1] out ;

    real sample, thresh ;

    analog begin
       ...
    end
endmodule

Have a look at the article "How to create a VerilogA model of a DAC with a variable width bus input"

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V00000911TpUAI&pageName=ArticleContent

Regards,

Very interesting. Thank you.

Very sorry for the late reply, I totally missed the cadence notification.
Your solution is great, I can't believe I didn't think of using a macro, this was what I was looking for.
Concerning the bus width, it may very well have been a typo in the reference manual, my bad for not looking at the code closer.

Thanks a lot Volker T and have a great day !

Unfortunately your link seems to ask for a Cadence Host ID which I do not have access to but regardless, I eventually found out on another forum that cadence's implementation of Verilog A in virtuoso doesn't allow for the port width to be a parameter while the original verilog A standard apparently does as highlighted in the reference manual.
Couldn't be a cadence product if they didn't find a way to make things harder then they should be : )
In any case, Volker's answer of using a macro perfectly fits my needs.

Thanks a lot for your input henker 

MC20250412421 said:

I eventually found out on another forum that cadence's implementation of Verilog A in virtuoso doesn't allow for the port width to be a parameter while the original verilog A standard apparently does as highlighted in the reference manual.
Couldn't be a cadence product if they didn't find a way to make things harder then they should be : )

Not strictly true (it's not that our implementation of VerilogA doesn't support the port width to be a parameter - it does). The challenge is that for this to work with ADE netlisting, you need to have a symbol with a parameterised bus width, and also the "shadow" database alongside the veriloga view to also have a parameterised bus width - this is so that the placed symbol and switch view match. OpenAccess itself (the database used by Virtuoso and many other industry tools) doesn't directly support parameterised bus widths, but instead we can make these parameterised cells which allows the bus width to be changed dynamically based on a parameter. That's exactly what the article that Volker pointed to does (I wrote it!). Yes, it's a little bit tricky but not too hard if you follow the article.

You might think this is just us making it harder than it should be, but it's really due to a limitation of the industry-standard database format.

The hostid you need (by the way) is the hostid of your license server - if you know where your license server is, you can log onto that and run "lmhostid" and then use that to register yourself. If you are having difficulty creating an account, email support@cadence.com for assistance in getting logged in.

Andrew

Thanks immensely Andrew Beckett !

I never knew about OpenAccess before so I understand the reason behind this design decision now. In any case, I was able to easily fix my issue using a macro. Having the port width as a parameter that can easily be set inside the schematic could potentially be something I'll look into further down the road. The parametrized cells seem like something that could come in handy for me.

I really value posts like yours because they shed light on what feels to me like a very obscure, corporate and proprietary software which is virtuoso.
I'll be transparent and mention that I am a university student who has been using cadence (mostly virtuoso) on university servers for about a year now so concerning the hostid, I'm afraid that's not something I really have access to. I also once asked cadence support a question about virtuoso and they refused to answer stating it was against the university agreement. Thankfully, these forums are open and I must thank you Andrew for all these posts you've done all these years, you really helped me immensely, more than you can think of. I can of course ask the EDA staff at my university but sometimes it's just quicker to use this forum.

Having said all this, as someone new to the EDA space and to Cadence, I must admit that my main gripe with the whole leaning experience is that finding support and good documentation for it feels needlessly hard. I needed some documentation for a SKILL script and some Analog Lib blocks and it was very hard to find inside your manuals and impossible to find online given how closed and secretive everything seems to be. I know cadence is a business and needs to sell online courses too but come on, I'm not asking you to become an open source project, just make my life easier trying to learn your product

Sorry for the rant, I guess much of what I perceive as being bad in cadence virtuoso mostly stems from my limited knowledge of it. These forums are great, they have already helped me so much so I'll probably be back eventually.

Thanks again Andrew and have a great day/evening !