Verilog A VACOMP-2032: Parameter for port width leads to error.

Hello,

I am trying to generate a block to use in my schematics which has a output port bus with a width defined by a parameter. To illustrate my problem I copied the code from a language reference manual for verilog A I found on the internet: https://www.siue.edu/~gengel/ece585WebStuff/OVI_VerilogA.pdf

This following code is the example at section 6-8 (page 94), it has a port "out" which has a width defined by the parameter bits=8.

`include "constants.vams"
`include "disciplines.vams"

module adc(in,out);

    parameter bits=8, fullscale=1.0, delay=0.0, ttime=10n ;
    input in ;
    output [0:bits-1] out ;
    electrical in, out ;
    real sample, thresh ;
    
    analog begin
        thresh = fullscale/2.0 ;
        generate i (bits-1,0) begin
            V(out[i]) <+ transition(sample > thresh, delay, ttime) ;
            if (sample > thresh) sample = sample - thresh ;
            sample = 2.0 * sample ;
        end
    end

endmodule

Building this module by clicking the button in the cadence verilog A text editor gives me the following error:

    Error found by spectre during AHDL compile.
    ERROR (VACOMP-2032):
        "/veriloga.va",
        line 6: The range specifications in the two declarations of the port
        'out' have different size, direction, or index. Provide the same range
        specification and rerun the simulation.
    ERROR (VACOMP-1816): Exiting AHDL compilation.

Is it possible to possible to define a port width as a parameter ? If so is there anything I can do to fix the code so that at the end I am able to generate a symbol to use in my schematics ?

Thanks in advance !